mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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4af77feab3
Document the ADC IP available on the RZ/G3S SoC. The ADC IP on the RZ/G3S differs slightly from the one found on the RZ/G2L. The identified differences are as follows: - different number of channels (one being used for temperature conversion); consequently, various registers differ; the temperature channel support was not available for the RZ/G2L variant; the #io-channel-cells property was added to be able to request the temperature channel from the thermal driver - different default sampling periods - the RZ/G3S variant lacks the ADVIC register. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Link: https://patch.msgid.link/20241206111337.726244-13-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
171 lines
3.4 KiB
YAML
171 lines
3.4 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/iio/adc/renesas,rzg2l-adc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas RZ/G2L ADC
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maintainers:
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- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
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description: |
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A/D Converter block is a successive approximation analog-to-digital converter
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with a 12-bit accuracy. Up to eight analog input channels can be selected.
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Conversions can be performed in single or repeat mode. Result of the ADC is
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stored in a 32-bit data register corresponding to each channel.
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- renesas,r9a07g043-adc # RZ/G2UL and RZ/Five
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- renesas,r9a07g044-adc # RZ/G2L
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- renesas,r9a07g054-adc # RZ/V2L
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- const: renesas,rzg2l-adc
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- items:
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- const: renesas,r9a08g045-adc # RZ/G3S
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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items:
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- description: converter clock
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- description: peripheral clock
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clock-names:
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items:
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- const: adclk
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- const: pclk
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power-domains:
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maxItems: 1
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resets:
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maxItems: 2
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reset-names:
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items:
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- const: presetn
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- const: adrst-n
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'#address-cells':
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const: 1
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'#size-cells':
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const: 0
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"#io-channel-cells":
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const: 1
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- power-domains
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- resets
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- reset-names
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patternProperties:
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"^channel@[0-8]$":
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$ref: adc.yaml
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type: object
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description: |
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Represents the external channels which are connected to the ADC.
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properties:
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reg:
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description: |
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The channel number.
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minimum: 0
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maximum: 8
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required:
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- reg
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additionalProperties: false
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: renesas,r9a07g043-adc
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then:
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patternProperties:
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"^channel@[2-8]$": false
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"^channel@[0-1]$":
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properties:
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reg:
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maximum: 1
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- if:
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properties:
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compatible:
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contains:
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enum:
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- renesas,r9a07g044-adc
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- renesas,r9a07g054-adc
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then:
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patternProperties:
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"^channel@[8]$": false
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"^channel@[0-7]$":
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properties:
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reg:
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maximum: 7
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/r9a07g044-cpg.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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adc: adc@10059000 {
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compatible = "renesas,r9a07g044-adc", "renesas,rzg2l-adc";
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reg = <0x10059000 0x400>;
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interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>;
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clocks = <&cpg CPG_MOD R9A07G044_ADC_ADCLK>,
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<&cpg CPG_MOD R9A07G044_ADC_PCLK>;
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clock-names = "adclk", "pclk";
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power-domains = <&cpg>;
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resets = <&cpg R9A07G044_ADC_PRESETN>,
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<&cpg R9A07G044_ADC_ADRST_N>;
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reset-names = "presetn", "adrst-n";
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#address-cells = <1>;
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#size-cells = <0>;
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channel@0 {
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reg = <0>;
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};
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channel@1 {
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reg = <1>;
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};
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channel@2 {
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reg = <2>;
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};
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channel@3 {
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reg = <3>;
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};
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channel@4 {
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reg = <4>;
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};
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channel@5 {
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reg = <5>;
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};
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channel@6 {
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reg = <6>;
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};
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channel@7 {
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reg = <7>;
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};
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};
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