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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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Add a new compatible and related bindings for the fpga-based AD408x AXI IP core, a variant of the generic AXI ADC IP. The AXI AD408x IP is a very similar HDL (fpga) variant of the generic AXI ADC IP, intended to control ad408x familiy. Although there are some particularities added for extended control of the ad408x devices such as the filter configuration. Wildcard naming is used to match the naming of the published firmware. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20250516082630.8236-5-antoniu.miclaus@analog.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
141 lines
3.6 KiB
YAML
141 lines
3.6 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/iio/adc/adi,axi-adc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Analog Devices AXI ADC IP core
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maintainers:
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- Michael Hennerich <michael.hennerich@analog.com>
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description: |
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Analog Devices Generic AXI ADC IP core for interfacing an ADC device
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with a high speed serial (JESD204B/C) or source synchronous parallel
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interface (LVDS/CMOS).
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Usually, some other interface type (i.e SPI) is used as a control
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interface for the actual ADC, while this IP core will interface
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to the data-lines of the ADC and handle the streaming of data into
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memory via DMA.
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In some cases, the AXI ADC interface is used to perform specialized
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operation to a particular ADC, e.g access the physical bus through
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specific registers to write ADC registers.
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In this case, we use a different compatible which indicates the target
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IP core's name.
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The following IP is currently supported:
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- AXI AD7606x: specialized version of the IP core for all the chips from
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the ad7606 family.
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https://wiki.analog.com/resources/fpga/docs/axi_adc_ip
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https://analogdevicesinc.github.io/hdl/library/axi_ad408x/index.html
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https://analogdevicesinc.github.io/hdl/library/axi_ad485x/index.html
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http://analogdevicesinc.github.io/hdl/library/axi_ad7606x/index.html
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properties:
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compatible:
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enum:
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- adi,axi-adc-10.0.a
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- adi,axi-ad408x
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- adi,axi-ad7606x
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- adi,axi-ad485x
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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dmas:
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maxItems: 1
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dma-names:
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items:
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- const: rx
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adi,adc-dev:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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A reference to a the actual ADC to which this FPGA ADC interfaces to.
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deprecated: true
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'#io-backend-cells':
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const: 0
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'#address-cells':
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const: 1
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'#size-cells':
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const: 0
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patternProperties:
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"^adc@[0-9a-f]+$":
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type: object
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properties:
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reg:
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maxItems: 1
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additionalProperties: true
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required:
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- compatible
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- reg
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required:
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- compatible
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- dmas
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- reg
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- clocks
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allOf:
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- if:
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properties:
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compatible:
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not:
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contains:
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const: adi,axi-ad7606x
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then:
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properties:
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'#address-cells': false
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'#size-cells': false
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patternProperties:
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"^adc@[0-9a-f]+$": false
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additionalProperties: false
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examples:
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- |
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adc@44a00000 {
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compatible = "adi,axi-adc-10.0.a";
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reg = <0x44a00000 0x10000>;
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dmas = <&rx_dma 0>;
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dma-names = "rx";
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clocks = <&axi_clk>;
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#io-backend-cells = <0>;
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};
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- |
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#include <dt-bindings/gpio/gpio.h>
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parallel_bus_controller@44a00000 {
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compatible = "adi,axi-ad7606x";
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reg = <0x44a00000 0x10000>;
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dmas = <&rx_dma 0>;
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dma-names = "rx";
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clocks = <&ext_clk>;
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#address-cells = <1>;
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#size-cells = <0>;
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adc@0 {
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compatible = "adi,ad7606b";
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reg = <0>;
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pwms = <&axi_pwm_gen 0 0>;
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pwm-names = "convst1";
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avcc-supply = <&adc_vref>;
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vdrive-supply = <&vdd_supply>;
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reset-gpios = <&gpio0 91 GPIO_ACTIVE_HIGH>;
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standby-gpios = <&gpio0 90 GPIO_ACTIVE_LOW>;
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adi,range-gpios = <&gpio0 89 GPIO_ACTIVE_HIGH>;
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adi,oversampling-ratio-gpios = <&gpio0 88 GPIO_ACTIVE_HIGH
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&gpio0 87 GPIO_ACTIVE_HIGH
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&gpio0 86 GPIO_ACTIVE_HIGH>;
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io-backends = <¶llel_bus_controller>;
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};
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};
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...
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