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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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903cc7096d
Specify the properties which are essential and which are not for the
Tegra I2C driver to function correctly. This was not added correctly when
the TXT binding was converted to yaml. All the existing DT nodes have
these properties already and hence this does not break the ABI.
dmas and dma-names which were specified as a must in the TXT binding
is now made optional since the driver can work in PIO mode if dmas are
missing.
Fixes: f10a9b722f ("dt-bindings: i2c: tegra: Convert to json-schema”)
Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Cc: <stable@vger.kernel.org> # v5.17+
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Andi Shyti <andi@smida.it>
Link: https://lore.kernel.org/r/20250603153022.39434-1-akhilrajeev@nvidia.com
212 lines
6.6 KiB
YAML
212 lines
6.6 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/i2c/nvidia,tegra20-i2c.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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maintainers:
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- Thierry Reding <thierry.reding@gmail.com>
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- Jon Hunter <jonathanh@nvidia.com>
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title: NVIDIA Tegra I2C controller driver
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properties:
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compatible:
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oneOf:
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- description: Tegra20 has 4 generic I2C controller. This can support
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master and slave mode of I2C communication. The i2c-tegra driver
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only support master mode of I2C communication. Driver of I2C
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controller is only compatible with "nvidia,tegra20-i2c".
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const: nvidia,tegra20-i2c
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- description: Tegra20 has specific I2C controller called as DVC I2C
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controller. This only support master mode of I2C communication.
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Register interface/offset and interrupts handling are different than
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generic I2C controller. Driver of DVC I2C controller is only
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compatible with "nvidia,tegra20-i2c-dvc".
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const: nvidia,tegra20-i2c-dvc
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- description: |
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Tegra30 has 5 generic I2C controller. This controller is very much
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similar to Tegra20 I2C controller with additional feature: Continue
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Transfer Support. This feature helps to implement M_NO_START as per
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I2C core API transfer flags. Driver of I2C controller is compatible
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with "nvidia,tegra30-i2c" to enable the continue transfer support.
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This is also compatible with "nvidia,tegra20-i2c" without continue
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transfer support.
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items:
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- const: nvidia,tegra30-i2c
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- const: nvidia,tegra20-i2c
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- description: |
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Tegra114 has 5 generic I2C controllers. This controller is very much
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similar to Tegra30 I2C controller with some hardware modification:
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- Tegra30/Tegra20 I2C controller has 2 clock source called div-clk
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and fast-clk. Tegra114 has only one clock source called as
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div-clk and hence clock mechanism is changed in I2C controller.
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- Tegra30/Tegra20 I2C controller has enabled per packet transfer
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by default and there is no way to disable it. Tegra114 has this
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interrupt disable by default and SW need to enable explicitly.
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Due to above changes, Tegra114 I2C driver makes incompatible with
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previous hardware driver. Hence, Tegra114 I2C controller is
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compatible with "nvidia,tegra114-i2c".
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const: nvidia,tegra114-i2c
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- description: |
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Tegra124 has 6 generic I2C controllers. These controllers are very
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similar to those found on Tegra114 but also contain several hardware
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improvements and new registers.
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const: nvidia,tegra124-i2c
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- description: |
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Tegra210 has 6 generic I2C controllers. These controllers are very
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similar to those found on Tegra124.
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items:
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- const: nvidia,tegra210-i2c
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- const: nvidia,tegra124-i2c
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- description: |
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Tegra210 has one I2C controller that is on host1x bus and is part of
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the VE power domain and typically used for camera use-cases. This VI
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I2C controller is mostly compatible with the programming model of
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the regular I2C controllers with a few exceptions. The I2C registers
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start at an offset of 0xc00 (instead of 0), registers are 16 bytes
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apart (rather than 4) and the controller does not support slave
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mode.
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const: nvidia,tegra210-i2c-vi
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- description: |
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Tegra186 has 9 generic I2C controllers, two of which are in the AON
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(always-on) partition of the SoC. All of these controllers are very
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similar to those found on Tegra210.
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const: nvidia,tegra186-i2c
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- description: |
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Tegra194 has 8 generic I2C controllers, two of which are in the AON
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(always-on) partition of the SoC. All of these controllers are very
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similar to those found on Tegra186. However, these controllers have
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support for 64 KiB transactions whereas earlier chips supported no
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more than 4 KiB per transactions.
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const: nvidia,tegra194-i2c
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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minItems: 1
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maxItems: 2
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clock-names:
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minItems: 1
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maxItems: 2
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resets:
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items:
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- description:
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Module reset. This property is optional for controllers in Tegra194,
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Tegra234 etc where an internal software reset is available as an
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alternative.
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reset-names:
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items:
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- const: i2c
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power-domains:
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maxItems: 1
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dmas:
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items:
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- description: DMA channel for the reception FIFO
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- description: DMA channel for the transmission FIFO
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dma-names:
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items:
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- const: rx
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- const: tx
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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allOf:
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- $ref: /schemas/i2c/i2c-controller.yaml
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- if:
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properties:
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compatible:
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contains:
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enum:
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- nvidia,tegra20-i2c
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- nvidia,tegra30-i2c
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then:
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properties:
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clocks:
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minItems: 2
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clock-names:
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items:
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- const: div-clk
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- const: fast-clk
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- if:
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properties:
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compatible:
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contains:
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enum:
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- nvidia,tegra114-i2c
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- nvidia,tegra210-i2c
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then:
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properties:
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clocks:
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maxItems: 1
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clock-names:
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items:
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- const: div-clk
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- if:
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properties:
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compatible:
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contains:
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const: nvidia,tegra210-i2c-vi
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then:
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properties:
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clocks:
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minItems: 2
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clock-names:
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items:
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- const: div-clk
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- const: slow
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power-domains:
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items:
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- description: phandle to the VENC power domain
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else:
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properties:
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power-domains: false
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- if:
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not:
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properties:
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compatible:
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contains:
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enum:
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- nvidia,tegra194-i2c
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then:
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required:
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- resets
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- reset-names
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unevaluatedProperties: false
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examples:
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- |
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i2c@7000c000 {
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compatible = "nvidia,tegra20-i2c";
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reg = <0x7000c000 0x100>;
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interrupts = <0 38 0x04>;
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clocks = <&tegra_car 12>, <&tegra_car 124>;
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clock-names = "div-clk", "fast-clk";
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resets = <&tegra_car 12>;
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reset-names = "i2c";
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dmas = <&apbdma 16>, <&apbdma 16>;
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dma-names = "rx", "tx";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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