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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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cc2f156a33
The GPIO controllers in most Rockchip SoCs are part of power domains that are always powered on, i.e. PD_BUS or PD_PMU. These always powered on power domains have typically not been described in the device tree. Because these power domains have been left out of the device tree there has not been any real need to properly describe the GPIO controllers power domain. On RK3528 the GPIO controllers are spread out among the described PD_RKVENC, PD_VO and PD_VPU power domains. However, one GPIO controller belong to an undescribed always powered on power domain. Add support to describe an optional power-domains for the GPIO controllers in Rockchip SoCs. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250723085654.2273324-2-jonas@kwiboo.se Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
100 lines
1.8 KiB
YAML
100 lines
1.8 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/gpio/rockchip,gpio-bank.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Rockchip GPIO bank
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maintainers:
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- Heiko Stuebner <heiko@sntech.de>
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properties:
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compatible:
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enum:
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- rockchip,gpio-bank
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- rockchip,rk3188-gpio-bank0
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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minItems: 1
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items:
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- description: APB interface clock source
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- description: GPIO debounce reference clock source
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gpio-ranges: true
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gpio-controller: true
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gpio-line-names: true
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"#gpio-cells":
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const: 2
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interrupt-controller: true
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"#interrupt-cells":
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const: 2
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power-domains:
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maxItems: 1
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patternProperties:
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"^.+-hog(-[0-9]+)?$":
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type: object
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required:
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- gpio-hog
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- gpio-controller
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- "#gpio-cells"
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- interrupt-controller
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- "#interrupt-cells"
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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pinctrl: pinctrl {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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gpio0: gpio@2000a000 {
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compatible = "rockchip,rk3188-gpio-bank0";
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reg = <0x2000a000 0x100>;
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interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_gates8 9>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio1: gpio@2003c000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x2003c000 0x100>;
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interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_gates8 10>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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