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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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338893af8e
This is a custom silicon GPIO driver provided by VeriSilicon Microelectronics. It has 32 input/output ports which can be configured as edge or level triggered interrupts. It also provides a de-bounce feature. This controller is used on the Blaize BLZP1600 SoC. Signed-off-by: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20250327-kernel-upstreaming-add_gpio_support-v2-1-bbe51f8d66da@blaize.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
78 lines
1.6 KiB
YAML
78 lines
1.6 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/gpio/blaize,blzp1600-gpio.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Blaize BLZP1600 GPIO controller
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description:
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Blaize BLZP1600 GPIO controller is an implementation of the VeriSilicon
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APB GPIO v0.2 IP block. It has 32 ports each of which are intended to be
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represented as child nodes with the generic GPIO-controller properties
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as described in this binding's file.
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maintainers:
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- Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
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- James Cowgill <james.cowgill@blaize.com>
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- Matt Redfearn <matt.redfearn@blaize.com>
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- Neil Jones <neil.jones@blaize.com>
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properties:
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$nodename:
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pattern: "^gpio@[0-9a-f]+$"
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compatible:
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enum:
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- blaize,blzp1600-gpio
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reg:
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maxItems: 1
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gpio-controller: true
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'#gpio-cells':
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const: 2
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ngpios:
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default: 32
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minimum: 1
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maximum: 32
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interrupts:
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maxItems: 1
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gpio-line-names: true
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interrupt-controller: true
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'#interrupt-cells':
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const: 2
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required:
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- compatible
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- reg
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- gpio-controller
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- '#gpio-cells'
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dependencies:
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interrupt-controller: [ interrupts ]
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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gpio: gpio@4c0000 {
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compatible = "blaize,blzp1600-gpio";
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reg = <0x004c0000 0x1000>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <32>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
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};
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...
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