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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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0121898ec0
DTS example in the bindings should be indented with 2- or 4-spaces and aligned with opening '- |', so correct any differences like 3-spaces or mixtures 2- and 4-spaces in one binding. No functional changes here, but saves some comments during reviews of new patches built on existing code. Acked-by: Ulf Hansson <ulf.hansson@linaro.org> # For MMC Acked-by: Lee Jones <lee@kernel.org> Acked-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> # renesas Link: https://lore.kernel.org/r/20250107131456.247610-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250725100241.120106-2-krzysztof.kozlowski@linaro.org Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
95 lines
2.9 KiB
YAML
95 lines
2.9 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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# Copyright 2019 Linaro Ltd.
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/firmware/intel,ixp4xx-network-processing-engine.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Intel IXP4xx Network Processing Engine
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maintainers:
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- Linus Walleij <linus.walleij@linaro.org>
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description: |
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On the IXP4xx SoCs, the Network Processing Engine (NPE) is a small
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processor that can load a firmware to perform offloading of networking
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and crypto tasks. It also manages the MDIO bus to the ethernet PHYs
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on the IXP4xx platform. All IXP4xx platforms have three NPEs at
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consecutive memory locations. They are all included in the same
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device node since they are not independent of each other.
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properties:
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compatible:
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oneOf:
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- items:
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- const: intel,ixp4xx-network-processing-engine
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reg:
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items:
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- description: NPE0 (NPE-A) register range
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- description: NPE1 (NPE-B) register range
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- description: NPE2 (NPE-C) register range
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crypto:
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$ref: /schemas/crypto/intel,ixp4xx-crypto.yaml#
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type: object
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description: Optional node for the embedded crypto engine, the node
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should be named with the instance number of the NPE engine used for
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the crypto engine.
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"#address-cells":
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const: 1
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"#size-cells":
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const: 0
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patternProperties:
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hss@[0-9]+$:
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$ref: /schemas/net/intel,ixp4xx-hss.yaml#
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type: object
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description: Optional node for the High Speed Serial link (HSS), the
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node should be named with the instance number of the NPE engine
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used for the HSS.
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/gpio/gpio.h>
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npe: npe@c8006000 {
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compatible = "intel,ixp4xx-network-processing-engine";
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reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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hss@0 {
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compatible = "intel,ixp4xx-hss";
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reg = <0>;
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intel,npe-handle = <&npe 0>;
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intel,queue-chl-rxtrig = <&qmgr 12>;
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intel,queue-chl-txready = <&qmgr 34>;
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intel,queue-pkt-rx = <&qmgr 13>;
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intel,queue-pkt-tx = <&qmgr 14>, <&qmgr 15>, <&qmgr 16>, <&qmgr 17>;
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intel,queue-pkt-rxfree = <&qmgr 18>, <&qmgr 19>, <&qmgr 20>, <&qmgr 21>;
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intel,queue-pkt-txdone = <&qmgr 22>;
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cts-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
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rts-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
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dcd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
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dtr-gpios = <&gpio_74 2 GPIO_ACTIVE_LOW>;
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clk-internal-gpios = <&gpio_74 0 GPIO_ACTIVE_HIGH>;
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};
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crypto {
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compatible = "intel,ixp4xx-crypto";
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intel,npe-handle = <&npe 2>;
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queue-rx = <&qmgr 30>;
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queue-txready = <&qmgr 29>;
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};
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};
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...
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