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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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9f149c5d6d
Add DT bindings for Microchip Azurite DPLL chip family. These chips provide up to 5 independent DPLL channels, 10 differential or single-ended inputs and 10 differential or 20 single-ended outputs. They can be connected via I2C or SPI busses. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Ivan Vecera <ivecera@redhat.com> Reviewed-by: Jiri Pirko <jiri@nvidia.com> Link: https://patch.msgid.link/20250704182202.1641943-3-ivecera@redhat.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
116 lines
2.5 KiB
YAML
116 lines
2.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/dpll/microchip,zl30731.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Microchip Azurite DPLL device
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maintainers:
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- Ivan Vecera <ivecera@redhat.com>
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description:
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Microchip Azurite DPLL (ZL3073x) is a family of DPLL devices that
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provides up to 5 independent DPLL channels, up to 10 differential or
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single-ended inputs and 10 differential or 20 single-ended outputs.
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These devices support both I2C and SPI interfaces.
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properties:
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compatible:
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enum:
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- microchip,zl30731
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- microchip,zl30732
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- microchip,zl30733
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- microchip,zl30734
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- microchip,zl30735
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reg:
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maxItems: 1
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required:
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- compatible
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- reg
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allOf:
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- $ref: /schemas/dpll/dpll-device.yaml#
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- $ref: /schemas/spi/spi-peripheral-props.yaml#
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unevaluatedProperties: false
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examples:
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- |
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i2c {
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#address-cells = <1>;
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#size-cells = <0>;
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dpll@70 {
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compatible = "microchip,zl30732";
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reg = <0x70>;
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dpll-types = "pps", "eec";
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input-pins {
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#address-cells = <1>;
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#size-cells = <0>;
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pin@0 { /* REF0P */
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reg = <0>;
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connection-type = "ext";
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label = "Input 0";
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supported-frequencies-hz = /bits/ 64 <1 1000>;
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};
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};
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output-pins {
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#address-cells = <1>;
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#size-cells = <0>;
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pin@3 { /* OUT1N */
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reg = <3>;
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connection-type = "gnss";
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esync-control;
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label = "Output 1";
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supported-frequencies-hz = /bits/ 64 <1 10000>;
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};
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};
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};
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};
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- |
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spi {
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#address-cells = <1>;
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#size-cells = <0>;
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dpll@70 {
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compatible = "microchip,zl30731";
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reg = <0x70>;
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spi-max-frequency = <12500000>;
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dpll-types = "pps";
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input-pins {
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#address-cells = <1>;
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#size-cells = <0>;
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pin@0 { /* REF0P */
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reg = <0>;
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connection-type = "ext";
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label = "Input 0";
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supported-frequencies-hz = /bits/ 64 <1 1000>;
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};
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};
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output-pins {
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#address-cells = <1>;
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#size-cells = <0>;
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pin@3 { /* OUT1N */
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reg = <3>;
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connection-type = "gnss";
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esync-control;
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label = "Output 1";
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supported-frequencies-hz = /bits/ 64 <1 10000>;
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};
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};
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};
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};
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...
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