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10cafa2d45
Cleanup by removing unneeded quotes from refs and redundant blank lines. No functional impact except adjusting to preferred coding style. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> # mediatek Acked-by: Rob Herring <robh@kernel.org> Acked-by: Hector Martin <marcan@marcan.st> # apple Acked-by: Paul Cercueil <paul@crapouillou.net> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> # Spear Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> # Renesas Reviewed-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> # Socionext Link: https://lore.kernel.org/r/20230124081117.31186-1-krzysztof.kozlowski@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
64 lines
1.4 KiB
YAML
64 lines
1.4 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/dma/socionext,uniphier-mio-dmac.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: UniPhier Media IO DMA controller
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description: |
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This works as an external DMA engine for SD/eMMC controllers etc.
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found in UniPhier LD4, Pro4, sLD8 SoCs.
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maintainers:
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- Masahiro Yamada <yamada.masahiro@socionext.com>
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allOf:
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- $ref: dma-controller.yaml#
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properties:
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compatible:
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const: socionext,uniphier-mio-dmac
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reg:
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maxItems: 1
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interrupts:
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description: |
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A list of interrupt specifiers associated with the DMA channels.
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The number of interrupt lines is SoC-dependent.
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clocks:
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maxItems: 1
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resets:
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maxItems: 1
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'#dma-cells':
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description: The single cell represents the channel index.
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const: 1
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- '#dma-cells'
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additionalProperties: false
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examples:
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- |
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// In the example below, "interrupts = <0 68 4>, <0 68 4>, ..." is not a
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// typo. The first two channels share a single interrupt line.
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dmac: dma-controller@5a000000 {
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compatible = "socionext,uniphier-mio-dmac";
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reg = <0x5a000000 0x1000>;
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interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,
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<0 71 4>, <0 72 4>, <0 73 4>, <0 74 4>;
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clocks = <&mio_clk 7>;
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resets = <&mio_rst 7>;
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#dma-cells = <1>;
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};
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