mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-08-31 22:23:05 +00:00
d2363272ef
Convert the Marvell MMP DMA binding to YAML. The TXT binding mentions that the controller may have one IRQ per DMA channel. Examples of this were dropped in the YAML binding because of dt_binding_check complaints (either too many interrupt cells or interrupts) and the fact that this is not used in any of the in-tree device trees. Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20240131-pxa-dma-yaml-v2-2-9611d0af0edc@skole.hr Signed-off-by: Vinod Koul <vkoul@kernel.org>
73 lines
1.4 KiB
YAML
73 lines
1.4 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
|
%YAML 1.2
|
|
---
|
|
$id: http://devicetree.org/schemas/dma/marvell,mmp-dma.yaml#
|
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
|
|
|
title: Marvell MMP DMA controller
|
|
|
|
maintainers:
|
|
- Duje Mihanović <duje.mihanovic@skole.hr>
|
|
|
|
description:
|
|
Marvell MMP SoCs may have two types of DMA controllers, peripheral and audio.
|
|
|
|
properties:
|
|
compatible:
|
|
enum:
|
|
- marvell,pdma-1.0
|
|
- marvell,adma-1.0
|
|
- marvell,pxa910-squ
|
|
|
|
reg:
|
|
maxItems: 1
|
|
|
|
interrupts:
|
|
description:
|
|
Interrupt lines for the controller, may be shared or one per DMA channel
|
|
minItems: 1
|
|
|
|
asram:
|
|
description:
|
|
A phandle to the SRAM pool
|
|
$ref: /schemas/types.yaml#/definitions/phandle
|
|
|
|
'#dma-channels':
|
|
deprecated: true
|
|
|
|
'#dma-requests':
|
|
deprecated: true
|
|
|
|
required:
|
|
- compatible
|
|
- reg
|
|
- interrupts
|
|
- '#dma-cells'
|
|
|
|
allOf:
|
|
- $ref: dma-controller.yaml#
|
|
- if:
|
|
properties:
|
|
compatible:
|
|
contains:
|
|
enum:
|
|
- marvell,pdma-1.0
|
|
then:
|
|
properties:
|
|
asram: false
|
|
else:
|
|
required:
|
|
- asram
|
|
|
|
unevaluatedProperties: false
|
|
|
|
examples:
|
|
- |
|
|
dma-controller@d4000000 {
|
|
compatible = "marvell,pdma-1.0";
|
|
reg = <0xd4000000 0x10000>;
|
|
interrupts = <47>;
|
|
#dma-cells = <2>;
|
|
dma-channels = <16>;
|
|
};
|