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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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90090f49f1
The OLDI transmitters (TXes) do not have registers of their own, and are
dependent on the source video-ports (VPs) from the DSS to provide
configuration data. This hardware doesn't directly sit on the internal
bus of the SoC, but does so via the DSS. Hence, the OLDI TXes are
supposed to be child nodes under the DSS, and not independent devices.
Two of the OLDI TXes can function in tandem to output dual-link OLDI
output, or cloned single-link outputs. In these cases, one OLDI will be
the primary OLDI, and the other one, a companion. The following diagram
represents such a configuration.
+-----+-----+ +-------+
| | | | |
| | VP1 +----+--->+ OLDI0 | (Primary - may need companion)
| | | | | |
| DSS +-----+ | +-------+
| | | |
| | VP2 | | +-------+
| | | | | |
+-----+-----+ +--->+ OLDI1 | (Companion OLDI)
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+-------+
The DSS in AM625 SoC has a configuration like the one above. The AM625
DSS VP1 (port@0) can connect and control 2 OLDI TXes, to use them in
dual-link or cloned single-link OLDI modes. It is only the VP1 that can
connect to either OLDI TXes for the AM625 DSS, and not the VP2.
Alternatively, on some future TI SoCs, along with the above
configuration, the OLDI TX can _also_ connect to separate video sources,
making them work entirely independent of each other. In this case,
neither of the OLDIs are "companion" or "secondary" OLDIs, and nor do
they require one. They both are independent and primary OLDIs. The
following diagram represents such a configuration.
+-----+-----+ +-------+
| | | | |
| | VP1 +--+----------->+ OLDI0 | (Primary - may need companion)
| | | | | |
| +-----+ | +-------+
| | | |
| | VP2 | |
| | | |
| DSS +-----+ | +---+ +-------+
| | | +-->+ M | | |
| | VP3 +----->+ U +--->+ OLDI1 | (Companion or Primary)
| | | | X | | |
| +-----+ +---+ +-------+
| | |
| | VP4 |
| | |
+-----+-----+
Note that depending on the mux configuration, the OLDIs can either be
working together in tandem - sourced by VP1, OR, they could be working
independently sourced by VP1 and VP3 respectively.
The idea is to support all the configurations with this OLDI TX schema.
The OLDI functionality is further supported by a system-control module,
which contains a few registers to control OLDI IO power and other
electrical characteristics of the IO lanes.
Add devicetree binding schema for the OLDI TXes to support various
configurations, and extend their support to the AM625 DSS.
Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com>
Signed-off-by: Aradhya Bhatia <aradhya.bhatia@linux.dev>
Reviewed-by: "Rob Herring (Arm)" <robh@kernel.org>
Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Link: https://lore.kernel.org/r/20250528122544.817829-3-aradhya.bhatia@linux.dev
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
350 lines
11 KiB
YAML
350 lines
11 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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# Copyright 2019 Texas Instruments Incorporated
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/ti/ti,am65x-dss.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Texas Instruments AM65x Display Subsystem
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maintainers:
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- Jyri Sarha <jsarha@ti.com>
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- Tomi Valkeinen <tomi.valkeinen@ti.com>
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description: |
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The AM625 and AM65x TI Keystone Display SubSystem has two output
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ports and two video planes. In AM65x DSS, the first video port
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supports 1 OLDI TX and in AM625 DSS, the first video port output is
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internally routed to 2 OLDI TXes. The second video port supports DPI
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format. The first plane is full video plane with all features and the
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second is a "lite plane" without scaling support.
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The AM62L display subsystem has a single output port which supports DPI
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format but it only supports single video "lite plane" which does not support
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scaling. The output port is routed to SoC boundary via DPI interface and same
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DPI signals are also routed internally to DSI Tx controller present within the
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SoC. Due to clocking limitations only one of the interface i.e. either DSI or
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DPI can be used at once.
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properties:
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compatible:
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enum:
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- ti,am625-dss
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- ti,am62a7-dss
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- ti,am62l-dss
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- ti,am65x-dss
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reg:
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description:
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Addresses to each DSS memory region described in the SoC's TRM.
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items:
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- description: common DSS register area
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- description: VIDL1 light video plane
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- description: VID video plane
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- description: OVR1 overlay manager for vp1
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- description: OVR2 overlay manager for vp2
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- description: VP1 video port 1
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- description: VP2 video port 2
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- description: common1 DSS register area
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reg-names:
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items:
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- const: common
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- const: vidl1
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- const: vid
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- const: ovr1
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- const: ovr2
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- const: vp1
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- const: vp2
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- const: common1
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clocks:
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items:
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- description: fck DSS functional clock
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- description: vp1 Video Port 1 pixel clock
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- description: vp2 Video Port 2 pixel clock
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clock-names:
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items:
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- const: fck
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- const: vp1
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- const: vp2
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assigned-clocks:
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minItems: 1
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maxItems: 3
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assigned-clock-parents:
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minItems: 1
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maxItems: 3
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interrupts:
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maxItems: 1
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power-domains:
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maxItems: 1
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description: phandle to the associated power domain
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dma-coherent:
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type: boolean
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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properties:
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port@0:
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$ref: /schemas/graph.yaml#/properties/port
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description:
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For AM65x DSS, the OLDI output port node from video port 1.
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For AM625 DSS, the internal DPI output port node from video
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port 1.
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For AM62A7 DSS, the port is tied off inside the SoC.
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For AM62L DSS, the DSS DPI output port node from video port 1
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or DSI Tx controller node connected to video port 1.
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properties:
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endpoint@0:
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$ref: /schemas/graph.yaml#/properties/endpoint
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description:
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For AM625 DSS, VP Connection to OLDI0.
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For AM65X DSS, OLDI output from the SoC.
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endpoint@1:
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$ref: /schemas/graph.yaml#/properties/endpoint
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description:
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For AM625 DSS, VP Connection to OLDI1.
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anyOf:
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- required:
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- endpoint
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- required:
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- endpoint@0
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- endpoint@1
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port@1:
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$ref: /schemas/graph.yaml#/properties/port
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description:
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The DSS DPI output port node from video port 2
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ti,am65x-oldi-io-ctrl:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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phandle to syscon device node mapping OLDI IO_CTRL registers.
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The mapped range should point to OLDI_DAT0_IO_CTRL, map it and
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following OLDI_DAT1_IO_CTRL, OLDI_DAT2_IO_CTRL, OLDI_DAT3_IO_CTRL,
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and OLDI_CLK_IO_CTRL registers. This property is needed for OLDI
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interface to work.
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max-memory-bandwidth:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Input memory (from main memory to dispc) bandwidth limit in
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bytes per second
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oldi-transmitters:
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description:
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Child node under the DSS, to describe all the OLDI transmitters connected
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to the DSS videoports.
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type: object
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additionalProperties: false
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properties:
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"#address-cells":
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const: 1
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"#size-cells":
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const: 0
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patternProperties:
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'^oldi@[0-1]$':
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$ref: ti,am625-oldi.yaml#
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description: OLDI transmitters connected to the DSS VPs
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: ti,am62a7-dss
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then:
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properties:
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oldi-transmitters: false
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ports:
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properties:
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port@0: false
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- if:
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properties:
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compatible:
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contains:
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const: ti,am62l-dss
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then:
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properties:
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ports:
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properties:
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port@1: false
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- if:
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properties:
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compatible:
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contains:
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enum:
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- ti,am62l-dss
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- ti,am65x-dss
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then:
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properties:
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oldi-transmitters: false
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ports:
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properties:
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port@0:
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properties:
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endpoint@1: false
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required:
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- compatible
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- reg
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- reg-names
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- clocks
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- clock-names
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- interrupts
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- ports
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/soc/ti,sci_pm_domain.h>
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dss: dss@4a00000 {
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compatible = "ti,am65x-dss";
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reg = <0x04a00000 0x1000>, /* common */
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<0x04a02000 0x1000>, /* vidl1 */
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<0x04a06000 0x1000>, /* vid */
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<0x04a07000 0x1000>, /* ovr1 */
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<0x04a08000 0x1000>, /* ovr2 */
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<0x04a0a000 0x1000>, /* vp1 */
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<0x04a0b000 0x1000>, /* vp2 */
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<0x04a01000 0x1000>; /* common1 */
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reg-names = "common", "vidl1", "vid",
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"ovr1", "ovr2", "vp1", "vp2", "common1";
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ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;
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power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 67 1>,
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<&k3_clks 216 1>,
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<&k3_clks 67 2>;
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clock-names = "fck", "vp1", "vp2";
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interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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oldi_out0: endpoint {
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remote-endpoint = <&lcd_in0>;
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};
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};
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};
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};
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/soc/ti,sci_pm_domain.h>
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bus {
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#address-cells = <2>;
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#size-cells = <2>;
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dss1: dss@30200000 {
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compatible = "ti,am625-dss";
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reg = <0x00 0x30200000 0x00 0x1000>, /* common */
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<0x00 0x30202000 0x00 0x1000>, /* vidl1 */
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<0x00 0x30206000 0x00 0x1000>, /* vid */
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<0x00 0x30207000 0x00 0x1000>, /* ovr1 */
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<0x00 0x30208000 0x00 0x1000>, /* ovr2 */
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<0x00 0x3020a000 0x00 0x1000>, /* vp1 */
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<0x00 0x3020b000 0x00 0x1000>, /* vp2 */
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<0x00 0x30201000 0x00 0x1000>; /* common1 */
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reg-names = "common", "vidl1", "vid",
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"ovr1", "ovr2", "vp1", "vp2", "common1";
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power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 186 6>,
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<&vp1_clock>,
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<&k3_clks 186 2>;
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clock-names = "fck", "vp1", "vp2";
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interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
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oldi-transmitters {
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#address-cells = <1>;
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#size-cells = <0>;
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oldi0: oldi@0 {
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reg = <0>;
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clocks = <&k3_clks 186 0>;
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clock-names = "serial";
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ti,companion-oldi = <&oldi1>;
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ti,oldi-io-ctrl = <&dss_oldi_io_ctrl>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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oldi0_in: endpoint {
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remote-endpoint = <&dpi0_out0>;
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};
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};
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port@1 {
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reg = <1>;
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oldi0_out: endpoint {
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remote-endpoint = <&panel_in0>;
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};
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};
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};
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};
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oldi1: oldi@1 {
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reg = <1>;
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clocks = <&k3_clks 186 0>;
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clock-names = "serial";
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ti,secondary-oldi;
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ti,companion-oldi = <&oldi0>;
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ti,oldi-io-ctrl = <&dss_oldi_io_ctrl>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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oldi1_in: endpoint {
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remote-endpoint = <&dpi0_out1>;
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};
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};
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port@1 {
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reg = <1>;
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oldi1_out: endpoint {
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remote-endpoint = <&panel_in1>;
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};
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};
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};
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};
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};
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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dpi0_out0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&oldi0_in>;
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};
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dpi0_out1: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&oldi1_in>;
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};
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};
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port@1 {
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reg = <1>;
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dpi1_out: endpoint {
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remote-endpoint = <&hdmi_bridge>;
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};
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};
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};
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};
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};
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