linux-loongson/Documentation/devicetree/bindings/display/sprd/sprd,sharkl3-dpu.yaml
Krzysztof Kozlowski 934da599e6 dt-bindings: display: sprd,sharkl3-dpu: Fix missing clocks constraints
'minItems' alone does not impose upper bound, unlike 'maxItems' which
implies lower bound.  Add missing clock constraint so the list will have
exact number of items (clocks).

Fixes: 8cae15c60c ("dt-bindings: display: add Unisoc's dpu bindings")
Cc: stable@vger.kernel.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250720123003.37662-3-krzysztof.kozlowski@linaro.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2025-07-22 23:14:14 -05:00

78 lines
1.6 KiB
YAML

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/sprd/sprd,sharkl3-dpu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Unisoc Sharkl3 Display Processor Unit (DPU)
maintainers:
- Kevin Tang <kevin.tang@unisoc.com>
description: |
DPU (Display Processor Unit) is the Display Controller for the Unisoc SoCs
which transfers the image data from a video memory buffer to an internal
LCD interface.
properties:
compatible:
const: sprd,sharkl3-dpu
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 2
clock-names:
items:
- const: clk_src_128m
- const: clk_src_384m
power-domains:
maxItems: 1
iommus:
maxItems: 1
port:
type: object
description:
A port node with endpoint definitions as defined in
Documentation/devicetree/bindings/media/video-interfaces.txt.
That port should be the output endpoint, usually output to
the associated DSI.
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- port
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/sprd,sc9860-clk.h>
dpu: dpu@63000000 {
compatible = "sprd,sharkl3-dpu";
reg = <0x63000000 0x1000>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "clk_src_128m", "clk_src_384m";
clocks = <&pll CLK_TWPLL_128M>,
<&pll CLK_TWPLL_384M>;
dpu_port: port {
dpu_out: endpoint {
remote-endpoint = <&dsi_in>;
};
};
};