mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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3832dc42ae
As with the RK3588 SoC, RK3576 also allows the use of HDMI PHY PLL as an
alternative and more accurate pixel clock source for VOP2.
Document the optional PLL clock property.
Moreover, given that this is part of a series intended to address some
recent display problems, provide the appropriate tags to facilitate
backporting.
Fixes: c3b7c5a4d7 ("dt-bindings: display: vop2: Add rk3576 support")
Cc: stable@vger.kernel.org
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Reviewed-by: "Rob Herring (Arm)" <robh@kernel.org>
Tested-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20250612-rk3576-hdmitx-fix-v1-1-4b11007d8675@collabora.com
316 lines
7.6 KiB
YAML
316 lines
7.6 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/rockchip/rockchip-vop2.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Rockchip SoC display controller (VOP2)
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description:
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VOP2 (Video Output Processor v2) is the display controller for the Rockchip
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series of SoCs which transfers the image data from a video memory buffer to
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an external LCD interface.
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maintainers:
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- Sandy Huang <hjc@rock-chips.com>
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- Heiko Stuebner <heiko@sntech.de>
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- Andy Yan <andyshrk@163.com>
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properties:
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compatible:
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enum:
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- rockchip,rk3566-vop
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- rockchip,rk3568-vop
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- rockchip,rk3576-vop
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- rockchip,rk3588-vop
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reg:
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items:
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- description:
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Must contain one entry corresponding to the base address and length
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of the register space.
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- description:
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Can optionally contain a second entry corresponding to the CRTC gamma
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LUT address.
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reg-names:
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items:
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- const: vop
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- const: gamma-lut
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interrupts:
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minItems: 1
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maxItems: 4
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description:
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For VOP version under rk3576, the interrupt is shared by several interrupt
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sources, such as frame start (VSYNC), line flag and other interrupt status.
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For VOP version from rk3576 there is a system interrupt for bus error, and
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every video port has it's independent interrupts for vsync and other video
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port related error interrupts.
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interrupt-names:
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items:
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- const: sys
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- const: vp0
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- const: vp1
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- const: vp2
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# See compatible-specific constraints below.
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clocks:
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minItems: 5
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items:
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- description: Clock for ddr buffer transfer via axi.
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- description: Clock for the ahb bus to R/W the regs.
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- description: Pixel clock for video port 0.
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- description: Pixel clock for video port 1.
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- description: Pixel clock for video port 2.
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- {}
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- {}
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- {}
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- {}
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clock-names:
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minItems: 5
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items:
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- const: aclk
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- const: hclk
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- const: dclk_vp0
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- const: dclk_vp1
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- const: dclk_vp2
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- {}
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- {}
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- {}
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- {}
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rockchip,grf:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Phandle to GRF regs used for control the polarity of dclk/hsync/vsync of DPI,
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also used for query vop memory bisr enable status, etc.
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rockchip,vo1-grf:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Phandle to VO GRF regs used for control the polarity of dclk/hsync/vsync of hdmi
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on rk3588.
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rockchip,vop-grf:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Phandle to VOP GRF regs used for control data path between vopr and hdmi/edp.
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rockchip,pmu:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Phandle to PMU GRF used for query vop memory bisr status on rk3588.
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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patternProperties:
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"^port@[0-3]$":
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$ref: /schemas/graph.yaml#/properties/port
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description: Output endpoint of VP0/1/2/3.
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required:
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- port@0
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unevaluatedProperties: false
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iommus:
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maxItems: 1
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power-domains:
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maxItems: 1
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required:
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- compatible
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- reg
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- reg-names
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- interrupts
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- clocks
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- clock-names
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- ports
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allOf:
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- if:
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properties:
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compatible:
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contains:
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enum:
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- rockchip,rk3566-vop
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- rockchip,rk3568-vop
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then:
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properties:
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clocks:
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maxItems: 5
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clock-names:
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maxItems: 5
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interrupts:
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maxItems: 1
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interrupt-names: false
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ports:
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required:
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- port@0
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- port@1
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- port@2
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rockchip,vo1-grf: false
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rockchip,vop-grf: false
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rockchip,pmu: false
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required:
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- rockchip,grf
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- if:
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properties:
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compatible:
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contains:
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enum:
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- rockchip,rk3576-vop
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then:
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properties:
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clocks:
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minItems: 5
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items:
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- {}
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- {}
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- {}
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- {}
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- {}
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- description: Alternative pixel clock provided by HDMI PHY PLL.
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clock-names:
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minItems: 5
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items:
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- {}
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- {}
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- {}
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- {}
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- {}
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- const: pll_hdmiphy0
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interrupts:
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minItems: 4
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interrupt-names:
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minItems: 4
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ports:
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required:
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- port@0
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- port@1
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- port@2
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rockchip,vo1-grf: false
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rockchip,vop-grf: false
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required:
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- rockchip,grf
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- rockchip,pmu
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- if:
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properties:
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compatible:
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contains:
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const: rockchip,rk3588-vop
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then:
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properties:
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clocks:
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minItems: 7
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items:
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- {}
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- {}
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- {}
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- {}
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- {}
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- description: Pixel clock for video port 3.
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- description: Peripheral(vop grf/dsi) clock.
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- description: Alternative pixel clock provided by HDMI0 PHY PLL.
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- description: Alternative pixel clock provided by HDMI1 PHY PLL.
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clock-names:
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minItems: 7
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items:
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- {}
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- {}
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- {}
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- {}
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- {}
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- const: dclk_vp3
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- const: pclk_vop
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- const: pll_hdmiphy0
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- const: pll_hdmiphy1
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interrupts:
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maxItems: 1
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interrupt-names: false
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ports:
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required:
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- port@0
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- port@1
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- port@2
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- port@3
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required:
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- rockchip,grf
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- rockchip,vo1-grf
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- rockchip,vop-grf
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- rockchip,pmu
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/rk3568-cru.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/rk3568-power.h>
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bus {
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#address-cells = <2>;
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#size-cells = <2>;
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vop: vop@fe040000 {
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compatible = "rockchip,rk3568-vop";
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reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>;
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reg-names = "vop", "gamma-lut";
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interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru ACLK_VOP>,
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<&cru HCLK_VOP>,
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<&cru DCLK_VOP0>,
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<&cru DCLK_VOP1>,
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<&cru DCLK_VOP2>;
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clock-names = "aclk",
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"hclk",
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"dclk_vp0",
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"dclk_vp1",
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"dclk_vp2";
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power-domains = <&power RK3568_PD_VO>;
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rockchip,grf = <&grf>;
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iommus = <&vop_mmu>;
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vop_out: ports {
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#address-cells = <1>;
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#size-cells = <0>;
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vp0: port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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vp1: port@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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vp2: port@2 {
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reg = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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};
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};
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