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The MIPI DBI 2.0 specification (2005) lists only two pixel formats for the Type C Interface (SPI) and that is 3-bits/pixel RGB111 with 2 options for bit layout. For Type A and B (parallel) the following formats are listed: RGB332, RGB444, RGB565, RGB666 and RGB888 (some have 2 options for the bit layout). Many MIPI DBI compatible controllers support all interface types on the same chip and often the manufacturers have chosen to provide support for the Type A/B interface pixel formats also on the Type C interface. Some chips provide many pixel formats with optional bit layouts over SPI, but the most common by far are RGB565 and RGB666. So even if the specification doesn't list these formats for the Type C interface, the industry has chosen to include them. The MIPI DCS specification lists the standard commands that can be sent over the MIPI DBI interface. The set_address_mode (36h) command has one bit in the parameter that controls RGB/BGR order: This bit controls the RGB data latching order transferred from the peripheral’s frame memory to the display device. This means that each supported RGB format also has a BGR variant. Based on this rationale document the following pixel formats describing the bit layout going over the wire: - RGB111 (option 1): x2r1g1b1r1g1b1 (2 pixels per byte) - BGR111 (option 1): x2b1g1r1b1g1r1 (2 pixels per byte) - RGB111 (option 2): x1r1g1b1x1r1g1b1 (2 pixels per byte) - BGR111 (option 2): x1b1g1r1x1b1g1r1 (2 pixels per byte) - RGB565: r5g6b5 (2 bytes) - BGR565: b5g6r5 (2 bytes) - RGB666: r6x2g6x2b6x2 (3 bytes) - BGR666: b6x2g6x2r6x2 (3 bytes) (x: don't care) v2: - Use 'default: r5g6b5' (Rob) Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patchwork.freedesktop.org/patch/msgid/20240604-panel-mipi-dbi-rgb666-v4-1-d7c2bcb9b78d@tronnes.org Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
172 lines
5.0 KiB
YAML
172 lines
5.0 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/panel/panel-mipi-dbi-spi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MIPI DBI SPI Panel
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maintainers:
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- Noralf Trønnes <noralf@tronnes.org>
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description: |
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This binding is for display panels using a MIPI DBI compatible controller
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in SPI mode.
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The MIPI Alliance Standard for Display Bus Interface defines the electrical
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and logical interfaces for display controllers historically used in mobile
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phones. The standard defines 4 display architecture types and this binding is
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for type 1 which has full frame memory. There are 3 interface types in the
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standard and type C is the serial interface.
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The standard defines the following interface signals for type C:
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- Power:
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- Vdd: Power supply for display module
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Called power-supply in this binding.
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- Vddi: Logic level supply for interface signals
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Called io-supply in this binding.
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- Interface:
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- CSx: Chip select
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- SCL: Serial clock
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- Dout: Serial out
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- Din: Serial in
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- SDA: Bidrectional in/out
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- D/CX: Data/command selection, high=data, low=command
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Called dc-gpios in this binding.
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- RESX: Reset when low
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Called reset-gpios in this binding.
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The type C interface has 3 options:
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- Option 1: 9-bit mode and D/CX as the 9th bit
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| Command | the next command or following data |
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|<0><D7><D6><D5><D4><D3><D2><D1><D0>|<D/CX><D7><D6><D5><D4><D3><D2><D1><D0>|
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- Option 2: 16-bit mode and D/CX as a 9th bit
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| Command or data |
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|<X><X><X><X><X><X><X><D/CX><D7><D6><D5><D4><D3><D2><D1><D0>|
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- Option 3: 8-bit mode and D/CX as a separate interface line
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| Command or data |
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|<D7><D6><D5><D4><D3><D2><D1><D0>|
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The standard defines one pixel format for type C: RGB111. The industry
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however has decided to provide the type A/B interface pixel formats also on
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the Type C interface and most common among these are RGB565 and RGB666.
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The MIPI DCS command set_address_mode (36h) has one bit that controls RGB/BGR
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order. This gives each supported RGB format a BGR variant.
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The panel resolution is specified using the panel-timing node properties
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hactive (width) and vactive (height). The other mandatory panel-timing
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properties should be set to zero except clock-frequency which can be
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optionally set to inform about the actual pixel clock frequency.
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If the panel is wired to the controller at an offset specify this using
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hback-porch (x-offset) and vback-porch (y-offset).
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allOf:
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- $ref: panel-common.yaml#
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- $ref: /schemas/spi/spi-peripheral-props.yaml#
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properties:
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compatible:
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items:
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- enum:
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- saef,sftc154b
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- sainsmart18
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- shineworld,lh133k
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- const: panel-mipi-dbi-spi
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reg:
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maxItems: 1
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write-only:
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type: boolean
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description:
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Controller is not readable (ie. Din (MISO on the SPI interface) is not
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wired up).
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dc-gpios:
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maxItems: 1
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description: |
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Controller data/command selection (D/CX) in 4-line SPI mode.
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If not set, the controller is in 3-line SPI mode.
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io-supply:
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description: |
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Logic level supply for interface signals (Vddi).
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No need to set if this is the same as power-supply.
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spi-3wire: true
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format:
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description: >
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Pixel format in bit order as going on the wire:
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* `x2r1g1b1r1g1b1` - RGB111, 2 pixels per byte
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* `x2b1g1r1b1g1r1` - BGR111, 2 pixels per byte
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* `x1r1g1b1x1r1g1b1` - RGB111, 2 pixels per byte
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* `x1b1g1r1x1b1g1r1` - BGR111, 2 pixels per byte
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* `r5g6b5` - RGB565, 2 bytes
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* `b5g6r5` - BGR565, 2 bytes
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* `r6x2g6x2b6x2` - RGB666, 3 bytes
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* `b6x2g6x2r6x2` - BGR666, 3 bytes
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enum:
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- x2r1g1b1r1g1b1
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- x2b1g1r1b1g1r1
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- x1r1g1b1x1r1g1b1
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- x1b1g1r1x1b1g1r1
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- r5g6b5
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- b5g6r5
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- r6x2g6x2b6x2
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- b6x2g6x2r6x2
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default: r5g6b5
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required:
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- compatible
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- reg
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- width-mm
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- height-mm
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- panel-timing
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/gpio/gpio.h>
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spi {
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#address-cells = <1>;
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#size-cells = <0>;
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display@0{
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compatible = "sainsmart18", "panel-mipi-dbi-spi";
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reg = <0>;
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spi-max-frequency = <40000000>;
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dc-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
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reset-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
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write-only;
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format = "r5g6b5";
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backlight = <&backlight>;
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width-mm = <35>;
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height-mm = <28>;
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panel-timing {
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hactive = <160>;
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vactive = <128>;
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hback-porch = <0>;
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vback-porch = <0>;
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clock-frequency = <0>;
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hfront-porch = <0>;
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hsync-len = <0>;
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vfront-porch = <0>;
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vsync-len = <0>;
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};
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};
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};
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...
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