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2b6433f30b
The display IPs in MediaTek SoCs support being interconnected with different instances of DDP IPs (for example, merge0 or merge1) and/or with different DDP IPs (for example, rdma can be connected with either color, dpi, dsi, merge, etc), forming a full Display Data Path that ends with an actual display. The final display pipeline is effectively board specific, as it does depend on the display that is attached to it, and eventually on the sensors supported by the board (for example, Adaptive Ambient Light would need an Ambient Light Sensor, otherwise it's pointless!), other than the output type. Add support for OF graphs to most of the MediaTek DDP (display) bindings to add flexibility to build custom hardware paths, hence enabling board specific configuration of the display pipeline and allowing to finally migrate away from using hardcoded paths. Please note that - while this commit retains retro-compatibility with old device trees - it will break the ABI for mediatek,dsi and for mediatek,dpi for the sake of consistency between the `ports` in all MediaTek DRM drivers versus DRM bridge drivers as in the previous binding, MediaTek was using `port` (implicitly, port@0) as an OUTPUT, while now the first port is an INPUT, and the second one is an OUTPUT, which is consistent with other DRM drivers which can be chained to drm/mediatek. As for maintainability concerns, I am aware that the old device tree will not be actively tested anymore, but retrocompatibility breakages will *not* be more likely to happen in the future because any addition to the graph (new drivers) will be done only for features present on newer SoCs, keeping the old ones (and their default pipeline) untouched. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Reviewed-by: CK Hu <ck.hu@mediatek.com> Tested-by: Michael Walle <mwalle@kernel.org> # on kontron-sbc-i1200 Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://patchwork.kernel.org/project/dri-devel/patch/20241017103809.156056-2-angelogioacchino.delregno@collabora.com/ Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
114 lines
3.3 KiB
YAML
114 lines
3.3 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/mediatek/mediatek,ovl-2l.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Mediatek display overlay 2 layer
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maintainers:
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- Chun-Kuang Hu <chunkuang.hu@kernel.org>
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- Philipp Zabel <p.zabel@pengutronix.de>
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description: |
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Mediatek display overlay 2 layer, namely OVL-2L, provides 2 more layer
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for OVL.
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OVL-2L device node must be siblings to the central MMSYS_CONFIG node.
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For a description of the MMSYS_CONFIG binding, see
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Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
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for details.
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properties:
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compatible:
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oneOf:
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- enum:
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- mediatek,mt8183-disp-ovl-2l
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- mediatek,mt8192-disp-ovl-2l
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- items:
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- enum:
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- mediatek,mt8186-disp-ovl-2l
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- const: mediatek,mt8192-disp-ovl-2l
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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power-domains:
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description: A phandle and PM domain specifier as defined by bindings of
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the power controller specified by phandle. See
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Documentation/devicetree/bindings/power/power-domain.yaml for details.
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clocks:
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items:
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- description: OVL-2L Clock
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iommus:
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description:
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This property should point to the respective IOMMU block with master port as argument,
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see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
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mediatek,gce-client-reg:
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description: The register of client driver can be configured by gce with
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4 arguments defined in this property, such as phandle of gce, subsys id,
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register offset and size. Each GCE subsys id is mapping to a client
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defined in the header include/dt-bindings/gce/<chip>-gce.h.
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$ref: /schemas/types.yaml#/definitions/phandle-array
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maxItems: 1
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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description:
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Input and output ports can have multiple endpoints, each of those
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connects to either the primary, secondary, etc, display pipeline.
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properties:
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port@0:
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$ref: /schemas/graph.yaml#/properties/port
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description: OVL input port from MMSYS, VDOSYS or other OVLs
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port@1:
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$ref: /schemas/graph.yaml#/properties/port
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description:
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OVL output to the input of the next desired component in the
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display pipeline, for example one of the available COLOR, RDMA
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or WDMA blocks.
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required:
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- port@0
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- port@1
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required:
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- compatible
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- reg
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- interrupts
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- power-domains
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- clocks
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- iommus
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/mt8183-clk.h>
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#include <dt-bindings/power/mt8183-power.h>
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#include <dt-bindings/gce/mt8183-gce.h>
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#include <dt-bindings/memory/mt8183-larb-port.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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ovl_2l0: ovl@14009000 {
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compatible = "mediatek,mt8183-disp-ovl-2l";
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reg = <0 0x14009000 0 0x1000>;
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interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
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clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
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iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>;
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mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
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};
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};
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