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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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2b6433f30b
The display IPs in MediaTek SoCs support being interconnected with different instances of DDP IPs (for example, merge0 or merge1) and/or with different DDP IPs (for example, rdma can be connected with either color, dpi, dsi, merge, etc), forming a full Display Data Path that ends with an actual display. The final display pipeline is effectively board specific, as it does depend on the display that is attached to it, and eventually on the sensors supported by the board (for example, Adaptive Ambient Light would need an Ambient Light Sensor, otherwise it's pointless!), other than the output type. Add support for OF graphs to most of the MediaTek DDP (display) bindings to add flexibility to build custom hardware paths, hence enabling board specific configuration of the display pipeline and allowing to finally migrate away from using hardcoded paths. Please note that - while this commit retains retro-compatibility with old device trees - it will break the ABI for mediatek,dsi and for mediatek,dpi for the sake of consistency between the `ports` in all MediaTek DRM drivers versus DRM bridge drivers as in the previous binding, MediaTek was using `port` (implicitly, port@0) as an OUTPUT, while now the first port is an INPUT, and the second one is an OUTPUT, which is consistent with other DRM drivers which can be chained to drm/mediatek. As for maintainability concerns, I am aware that the old device tree will not be actively tested anymore, but retrocompatibility breakages will *not* be more likely to happen in the future because any addition to the graph (new drivers) will be done only for features present on newer SoCs, keeping the old ones (and their default pipeline) untouched. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Reviewed-by: CK Hu <ck.hu@mediatek.com> Tested-by: Michael Walle <mwalle@kernel.org> # on kontron-sbc-i1200 Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://patchwork.kernel.org/project/dri-devel/patch/20241017103809.156056-2-angelogioacchino.delregno@collabora.com/ Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
209 lines
7.4 KiB
YAML
209 lines
7.4 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/mediatek/mediatek,ethdr.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek Ethdr Device
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maintainers:
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- Chun-Kuang Hu <chunkuang.hu@kernel.org>
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- Philipp Zabel <p.zabel@pengutronix.de>
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description:
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ETHDR (ET High Dynamic Range) is a MediaTek internal HDR engine and is
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designed for HDR video and graphics conversion in the external display path.
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It handles multiple HDR input types and performs tone mapping, color
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space/color format conversion, and then combine different layers,
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output the required HDR or SDR signal to the subsequent display path.
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This engine is composed of two video frontends, two graphic frontends,
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one video backend and a mixer. ETHDR has two DMA function blocks, DS and ADL.
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These two function blocks read the pre-programmed registers from DRAM and
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set them to HW in the v-blanking period.
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properties:
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compatible:
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oneOf:
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- const: mediatek,mt8195-disp-ethdr
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- items:
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- const: mediatek,mt8188-disp-ethdr
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- const: mediatek,mt8195-disp-ethdr
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reg:
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maxItems: 7
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reg-names:
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items:
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- const: mixer
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- const: vdo_fe0
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- const: vdo_fe1
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- const: gfx_fe0
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- const: gfx_fe1
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- const: vdo_be
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- const: adl_ds
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interrupts:
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maxItems: 1
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iommus:
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minItems: 1
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maxItems: 2
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clocks:
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items:
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- description: mixer clock
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- description: video frontend 0 clock
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- description: video frontend 1 clock
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- description: graphic frontend 0 clock
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- description: graphic frontend 1 clock
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- description: video backend clock
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- description: autodownload and menuload clock
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- description: video frontend 0 async clock
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- description: video frontend 1 async clock
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- description: graphic frontend 0 async clock
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- description: graphic frontend 1 async clock
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- description: video backend async clock
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- description: ethdr top clock
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clock-names:
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items:
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- const: mixer
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- const: vdo_fe0
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- const: vdo_fe1
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- const: gfx_fe0
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- const: gfx_fe1
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- const: vdo_be
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- const: adl_ds
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- const: vdo_fe0_async
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- const: vdo_fe1_async
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- const: gfx_fe0_async
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- const: gfx_fe1_async
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- const: vdo_be_async
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- const: ethdr_top
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power-domains:
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maxItems: 1
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resets:
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items:
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- description: video frontend 0 async reset
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- description: video frontend 1 async reset
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- description: graphic frontend 0 async reset
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- description: graphic frontend 1 async reset
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- description: video backend async reset
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reset-names:
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items:
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- const: vdo_fe0_async
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- const: vdo_fe1_async
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- const: gfx_fe0_async
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- const: gfx_fe1_async
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- const: vdo_be_async
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mediatek,gce-client-reg:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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minItems: 1
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maxItems: 7
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description: The register of display function block to be set by gce.
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There are 4 arguments in this property, gce node, subsys id, offset and
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register size. The subsys id is defined in the gce header of each chips
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include/dt-bindings/gce/<chip>-gce.h, mapping to the register of display
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function block.
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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description:
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Input and output ports can have multiple endpoints, each of those
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connects to either the primary, secondary, etc, display pipeline.
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properties:
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port@0:
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$ref: /schemas/graph.yaml#/properties/port
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description: ETHDR input, usually from one of the MERGE blocks.
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port@1:
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$ref: /schemas/graph.yaml#/properties/port
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description:
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ETHDR output to the input of the next desired component in the
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display pipeline, for example one of the available MERGE blocks,
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or others.
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required:
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- port@0
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- port@1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- interrupts
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- power-domains
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- resets
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- mediatek,gce-client-reg
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/mt8195-clk.h>
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#include <dt-bindings/gce/mt8195-gce.h>
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#include <dt-bindings/memory/mt8195-memory-port.h>
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#include <dt-bindings/power/mt8195-power.h>
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#include <dt-bindings/reset/mt8195-resets.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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hdr-engine@1c114000 {
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compatible = "mediatek,mt8195-disp-ethdr";
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reg = <0 0x1c114000 0 0x1000>,
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<0 0x1c115000 0 0x1000>,
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<0 0x1c117000 0 0x1000>,
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<0 0x1c119000 0 0x1000>,
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<0 0x1c11a000 0 0x1000>,
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<0 0x1c11b000 0 0x1000>,
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<0 0x1c11c000 0 0x1000>;
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reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
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"vdo_be", "adl_ds";
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mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>,
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<&gce0 SUBSYS_1c11XXXX 0x5000 0x1000>,
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<&gce0 SUBSYS_1c11XXXX 0x7000 0x1000>,
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<&gce0 SUBSYS_1c11XXXX 0x9000 0x1000>,
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<&gce0 SUBSYS_1c11XXXX 0xa000 0x1000>,
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<&gce0 SUBSYS_1c11XXXX 0xb000 0x1000>,
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<&gce0 SUBSYS_1c11XXXX 0xc000 0x1000>;
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clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
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<&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
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<&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
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<&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
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<&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
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<&vdosys1 CLK_VDO1_HDR_VDO_BE>,
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<&vdosys1 CLK_VDO1_26M_SLOW>,
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<&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
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<&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
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<&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
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<&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
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<&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
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<&topckgen CLK_TOP_ETHDR>;
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clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
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"vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async",
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"gfx_fe0_async", "gfx_fe1_async","vdo_be_async",
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"ethdr_top";
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power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
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iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,
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<&iommu_vpp M4U_PORT_L3_HDR_ADL>;
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interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */
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resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>,
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<&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>,
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<&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>,
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<&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>,
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<&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>;
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reset-names = "vdo_fe0_async", "vdo_fe1_async", "gfx_fe0_async",
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"gfx_fe1_async", "vdo_be_async";
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};
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};
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...
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