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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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2b6433f30b
The display IPs in MediaTek SoCs support being interconnected with different instances of DDP IPs (for example, merge0 or merge1) and/or with different DDP IPs (for example, rdma can be connected with either color, dpi, dsi, merge, etc), forming a full Display Data Path that ends with an actual display. The final display pipeline is effectively board specific, as it does depend on the display that is attached to it, and eventually on the sensors supported by the board (for example, Adaptive Ambient Light would need an Ambient Light Sensor, otherwise it's pointless!), other than the output type. Add support for OF graphs to most of the MediaTek DDP (display) bindings to add flexibility to build custom hardware paths, hence enabling board specific configuration of the display pipeline and allowing to finally migrate away from using hardcoded paths. Please note that - while this commit retains retro-compatibility with old device trees - it will break the ABI for mediatek,dsi and for mediatek,dpi for the sake of consistency between the `ports` in all MediaTek DRM drivers versus DRM bridge drivers as in the previous binding, MediaTek was using `port` (implicitly, port@0) as an OUTPUT, while now the first port is an INPUT, and the second one is an OUTPUT, which is consistent with other DRM drivers which can be chained to drm/mediatek. As for maintainability concerns, I am aware that the old device tree will not be actively tested anymore, but retrocompatibility breakages will *not* be more likely to happen in the future because any addition to the graph (new drivers) will be done only for features present on newer SoCs, keeping the old ones (and their default pipeline) untouched. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Tested-by: Alexandre Mergnat <amergnat@baylibre.com> Reviewed-by: CK Hu <ck.hu@mediatek.com> Tested-by: Michael Walle <mwalle@kernel.org> # on kontron-sbc-i1200 Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://patchwork.kernel.org/project/dri-devel/patch/20241017103809.156056-2-angelogioacchino.delregno@collabora.com/ Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
152 lines
3.5 KiB
YAML
152 lines
3.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/mediatek/mediatek,dsi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek DSI Controller
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maintainers:
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- Chun-Kuang Hu <chunkuang.hu@kernel.org>
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- Philipp Zabel <p.zabel@pengutronix.de>
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- Jitao Shi <jitao.shi@mediatek.com>
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description: |
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The MediaTek DSI function block is a sink of the display subsystem and can
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drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
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channel output.
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allOf:
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- $ref: /schemas/display/dsi-controller.yaml#
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properties:
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compatible:
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oneOf:
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- enum:
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- mediatek,mt2701-dsi
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- mediatek,mt7623-dsi
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- mediatek,mt8167-dsi
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- mediatek,mt8173-dsi
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- mediatek,mt8183-dsi
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- mediatek,mt8186-dsi
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- mediatek,mt8188-dsi
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- items:
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- enum:
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- mediatek,mt6795-dsi
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- const: mediatek,mt8173-dsi
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- items:
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- enum:
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- mediatek,mt8195-dsi
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- mediatek,mt8365-dsi
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- const: mediatek,mt8183-dsi
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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power-domains:
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maxItems: 1
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clocks:
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items:
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- description: Engine Clock
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- description: Digital Clock
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- description: HS Clock
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clock-names:
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items:
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- const: engine
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- const: digital
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- const: hs
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resets:
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maxItems: 1
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phys:
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maxItems: 1
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phy-names:
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items:
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- const: dphy
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port:
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$ref: /schemas/graph.yaml#/properties/port
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description:
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Output port node. This port should be connected to the input
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port of an attached DSI panel or DSI-to-eDP encoder chip.
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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description:
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Input ports can have multiple endpoints, each of those connects
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to either the primary, secondary, etc, display pipeline.
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properties:
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port@0:
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$ref: /schemas/graph.yaml#/properties/port
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description: DSI input port, usually from DITHER, DSC or MERGE
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port@1:
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$ref: /schemas/graph.yaml#/properties/port
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description:
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DSI output to an attached DSI panel, or a DSI-to-X encoder chip
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required:
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- port@0
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- port@1
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required:
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- compatible
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- reg
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- interrupts
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- power-domains
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- clocks
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- clock-names
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- phys
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- phy-names
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oneOf:
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- required:
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- port
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- required:
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- ports
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/mt8183-clk.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/power/mt8183-power.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/reset/mt8183-resets.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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dsi0: dsi@14014000 {
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compatible = "mediatek,mt8183-dsi";
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reg = <0 0x14014000 0 0x1000>;
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interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
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clocks = <&mmsys CLK_MM_DSI0_MM>,
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<&mmsys CLK_MM_DSI0_IF>,
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<&mipi_tx0>;
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clock-names = "engine", "digital", "hs";
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resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>;
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phys = <&mipi_tx0>;
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phy-names = "dphy";
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port {
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dsi0_out: endpoint {
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remote-endpoint = <&panel_in>;
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};
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};
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};
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};
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...
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