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i.MX8qxp Display Controller(DC) is comprised of three main components that include a blit engine for 2D graphics accelerations, display controller for display output processing, as well as a command sequencer. Signed-off-by: Liu Ying <victor.liu@nxp.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250414035028.1561475-9-victor.liu@nxp.com
237 lines
8.6 KiB
YAML
237 lines
8.6 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale i.MX8qxp Display Controller
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description: |
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The Freescale i.MX8qxp Display Controller(DC) is comprised of three main
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components that include a blit engine for 2D graphics accelerations, display
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controller for display output processing, as well as a command sequencer.
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Display buffers Source buffers
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(AXI read master) (AXI read master)
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| .......... | | | |
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+---------------------------+------------+------------------+-+-+------+
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| Display Controller (DC) | .......... | | | | |
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| | | | | | |
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| @@@@@@@@@@@ +----------+------------+------------+ | | | |
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A | | Command | | V V | | | | |
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X <-+->| Sequencer | | @@@@@@@@@@@@@@@@@@@@@@@@@@@@ | V V V |
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I | | (AXI CLK) | | | | | @@@@@@@@@@ |
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| @@@@@@@@@@@ | | Pixel Engine | | | | |
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| | | | (AXI CLK) | | | | |
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| V | @@@@@@@@@@@@@@@@@@@@@@@@@@@@ | | | |
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A | *********** | | | | | | | Blit | |
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H <-+->| Configure | | V V V V | | Engine | |
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B | | (CFG CLK) | | 00000000000 11111111111 | | (AXI CLK)| |
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| *********** | | Display | | Display | | | | |
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| | | Engine | | Engine | | | | |
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| | | (Disp CLK)| | (Disp CLK)| | | | |
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| @@@@@@@@@@@ | 00000000000 11111111111 | @@@@@@@@@@ |
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I | | Common | | | | | | |
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R <-+--| Control | | | Display | | | |
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Q | | (AXI CLK) | | | Controller | | | |
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| @@@@@@@@@@@ +------------------------------------+ | |
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| | | ^ | |
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+--------------------------+----------------+-------+---------+--------+
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^ | | | |
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| V V | V
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Clocks & Resets Display Display Panic Destination
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Output0 Output1 Control buffer
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(AXI write master)
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maintainers:
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- Liu Ying <victor.liu@nxp.com>
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properties:
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compatible:
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const: fsl,imx8qxp-dc
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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resets:
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maxItems: 2
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reset-names:
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items:
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- const: axi
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- const: cfg
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power-domains:
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maxItems: 1
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"#address-cells":
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const: 1
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"#size-cells":
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const: 1
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ranges: true
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patternProperties:
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"^command-sequencer@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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const: fsl,imx8qxp-dc-command-sequencer
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"^display-engine@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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const: fsl,imx8qxp-dc-display-engine
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"^interrupt-controller@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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const: fsl,imx8qxp-dc-intc
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"^pixel-engine@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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const: fsl,imx8qxp-dc-pixel-engine
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"^pmu@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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const: fsl,imx8qxp-dc-axi-performance-counter
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required:
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- compatible
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- reg
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- clocks
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- power-domains
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- "#address-cells"
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- "#size-cells"
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- ranges
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/imx8-lpcg.h>
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#include <dt-bindings/firmware/imx/rsrc.h>
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display-controller@56180000 {
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compatible = "fsl,imx8qxp-dc";
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reg = <0x56180000 0x40000>;
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clocks = <&dc0_lpcg IMX_LPCG_CLK_4>;
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power-domains = <&pd IMX_SC_R_DC_0>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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interrupt-controller@56180040 {
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compatible = "fsl,imx8qxp-dc-intc";
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reg = <0x56180040 0x60>;
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clocks = <&dc0_lpcg IMX_LPCG_CLK_5>;
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interrupt-controller;
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interrupt-parent = <&dc0_irqsteer>;
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#interrupt-cells = <1>;
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interrupts = <448>, <449>, <450>, <64>,
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<65>, <66>, <67>, <68>,
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<69>, <70>, <193>, <194>,
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<195>, <196>, <197>, <72>,
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<73>, <74>, <75>, <76>,
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<77>, <78>, <79>, <80>,
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<81>, <199>, <200>, <201>,
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<202>, <203>, <204>, <205>,
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<206>, <207>, <208>, <5>,
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<0>, <1>, <2>, <3>,
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<4>, <82>, <83>, <84>,
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<85>, <209>, <210>, <211>,
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<212>;
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interrupt-names = "store9_shdload",
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"store9_framecomplete",
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"store9_seqcomplete",
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"extdst0_shdload",
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"extdst0_framecomplete",
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"extdst0_seqcomplete",
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"extdst4_shdload",
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"extdst4_framecomplete",
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"extdst4_seqcomplete",
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"extdst1_shdload",
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"extdst1_framecomplete",
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"extdst1_seqcomplete",
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"extdst5_shdload",
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"extdst5_framecomplete",
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"extdst5_seqcomplete",
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"disengcfg_shdload0",
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"disengcfg_framecomplete0",
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"disengcfg_seqcomplete0",
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"framegen0_int0",
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"framegen0_int1",
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"framegen0_int2",
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"framegen0_int3",
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"sig0_shdload",
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"sig0_valid",
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"sig0_error",
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"disengcfg_shdload1",
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"disengcfg_framecomplete1",
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"disengcfg_seqcomplete1",
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"framegen1_int0",
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"framegen1_int1",
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"framegen1_int2",
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"framegen1_int3",
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"sig1_shdload",
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"sig1_valid",
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"sig1_error",
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"reserved",
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"cmdseq_error",
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"comctrl_sw0",
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"comctrl_sw1",
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"comctrl_sw2",
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"comctrl_sw3",
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"framegen0_primsync_on",
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"framegen0_primsync_off",
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"framegen0_secsync_on",
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"framegen0_secsync_off",
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"framegen1_primsync_on",
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"framegen1_primsync_off",
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"framegen1_secsync_on",
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"framegen1_secsync_off";
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};
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pixel-engine@56180800 {
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compatible = "fsl,imx8qxp-dc-pixel-engine";
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reg = <0x56180800 0xac00>;
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clocks = <&dc0_lpcg IMX_LPCG_CLK_5>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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};
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display-engine@5618b400 {
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compatible = "fsl,imx8qxp-dc-display-engine";
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reg = <0x5618b400 0x14>, <0x5618b800 0x1c00>;
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reg-names = "top", "cfg";
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interrupt-parent = <&dc0_intc>;
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interrupts = <15>, <16>, <17>;
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interrupt-names = "shdload", "framecomplete", "seqcomplete";
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power-domains = <&pd IMX_SC_R_DC_0_PLL_0>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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};
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};
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