mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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69c78e7e8c
i.MX8qxp Display Controller pixel engine consists of all processing units that operate in the AXI bus clock domain. Command sequencer and interrupt controller of the Display Controller work with AXI bus clock, but they are not in pixel engine. Signed-off-by: Liu Ying <victor.liu@nxp.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250414035028.1561475-5-victor.liu@nxp.com
251 lines
6.2 KiB
YAML
251 lines
6.2 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-pixel-engine.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale i.MX8qxp Display Controller Pixel Engine
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description:
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All Processing Units that operate in the AXI bus clock domain. Pixel
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pipelines have the ability to stall when a destination is busy. Implements
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all communication to memory resources and most of the image processing
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functions. Interconnection of Processing Units is re-configurable.
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maintainers:
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- Liu Ying <victor.liu@nxp.com>
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properties:
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compatible:
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const: fsl,imx8qxp-dc-pixel-engine
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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"#address-cells":
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const: 1
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"#size-cells":
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const: 1
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ranges: true
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patternProperties:
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"^blit-engine@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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const: fsl,imx8qxp-dc-blit-engine
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"^constframe@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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const: fsl,imx8qxp-dc-constframe
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"^extdst@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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const: fsl,imx8qxp-dc-extdst
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"^fetchdecode@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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const: fsl,imx8qxp-dc-fetchdecode
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"^fetcheco@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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const: fsl,imx8qxp-dc-fetcheco
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"^fetchlayer@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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const: fsl,imx8qxp-dc-fetchlayer
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"^fetchwarp@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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const: fsl,imx8qxp-dc-fetchwarp
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"^hscaler@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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const: fsl,imx8qxp-dc-hscaler
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"^layerblend@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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const: fsl,imx8qxp-dc-layerblend
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"^matrix@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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const: fsl,imx8qxp-dc-matrix
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"^safety@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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const: fsl,imx8qxp-dc-safety
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"^vscaler@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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const: fsl,imx8qxp-dc-vscaler
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required:
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- compatible
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- reg
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- clocks
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- "#address-cells"
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- "#size-cells"
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- ranges
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/imx8-lpcg.h>
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pixel-engine@56180800 {
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compatible = "fsl,imx8qxp-dc-pixel-engine";
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reg = <0x56180800 0xac00>;
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clocks = <&dc0_lpcg IMX_LPCG_CLK_5>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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constframe@56180960 {
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compatible = "fsl,imx8qxp-dc-constframe";
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reg = <0x56180960 0xc>, <0x56184400 0x20>;
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reg-names = "pec", "cfg";
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};
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extdst@56180980 {
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compatible = "fsl,imx8qxp-dc-extdst";
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reg = <0x56180980 0x1c>, <0x56184800 0x28>;
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reg-names = "pec", "cfg";
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interrupt-parent = <&dc0_intc>;
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interrupts = <3>, <4>, <5>;
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interrupt-names = "shdload", "framecomplete", "seqcomplete";
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};
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constframe@561809a0 {
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compatible = "fsl,imx8qxp-dc-constframe";
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reg = <0x561809a0 0xc>, <0x56184c00 0x20>;
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reg-names = "pec", "cfg";
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};
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extdst@561809c0 {
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compatible = "fsl,imx8qxp-dc-extdst";
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reg = <0x561809c0 0x1c>, <0x56185000 0x28>;
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reg-names = "pec", "cfg";
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interrupt-parent = <&dc0_intc>;
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interrupts = <6>, <7>, <8>;
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interrupt-names = "shdload", "framecomplete", "seqcomplete";
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};
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constframe@561809e0 {
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compatible = "fsl,imx8qxp-dc-constframe";
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reg = <0x561809e0 0xc>, <0x56185400 0x20>;
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reg-names = "pec", "cfg";
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};
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extdst@56180a00 {
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compatible = "fsl,imx8qxp-dc-extdst";
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reg = <0x56180a00 0x1c>, <0x56185800 0x28>;
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reg-names = "pec", "cfg";
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interrupt-parent = <&dc0_intc>;
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interrupts = <9>, <10>, <11>;
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interrupt-names = "shdload", "framecomplete", "seqcomplete";
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};
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constframe@56180a20 {
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compatible = "fsl,imx8qxp-dc-constframe";
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reg = <0x56180a20 0xc>, <0x56185c00 0x20>;
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reg-names = "pec", "cfg";
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};
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extdst@56180a40 {
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compatible = "fsl,imx8qxp-dc-extdst";
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reg = <0x56180a40 0x1c>, <0x56186000 0x28>;
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reg-names = "pec", "cfg";
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interrupt-parent = <&dc0_intc>;
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interrupts = <12>, <13>, <14>;
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interrupt-names = "shdload", "framecomplete", "seqcomplete";
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};
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fetchwarp@56180a60 {
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compatible = "fsl,imx8qxp-dc-fetchwarp";
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reg = <0x56180a60 0x10>, <0x56186400 0x190>;
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reg-names = "pec", "cfg";
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};
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fetchlayer@56180ac0 {
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compatible = "fsl,imx8qxp-dc-fetchlayer";
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reg = <0x56180ac0 0xc>, <0x56188400 0x404>;
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reg-names = "pec", "cfg";
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};
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layerblend@56180ba0 {
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compatible = "fsl,imx8qxp-dc-layerblend";
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reg = <0x56180ba0 0x10>, <0x5618a400 0x20>;
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reg-names = "pec", "cfg";
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};
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layerblend@56180bc0 {
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compatible = "fsl,imx8qxp-dc-layerblend";
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reg = <0x56180bc0 0x10>, <0x5618a800 0x20>;
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reg-names = "pec", "cfg";
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};
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layerblend@56180be0 {
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compatible = "fsl,imx8qxp-dc-layerblend";
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reg = <0x56180be0 0x10>, <0x5618ac00 0x20>;
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reg-names = "pec", "cfg";
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};
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layerblend@56180c00 {
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compatible = "fsl,imx8qxp-dc-layerblend";
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reg = <0x56180c00 0x10>, <0x5618b000 0x20>;
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reg-names = "pec", "cfg";
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};
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};
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