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c809469f25
i.MX8qxp Display Controller contains a command sequencer is designed to autonomously process command lists. Signed-off-by: Liu Ying <victor.liu@nxp.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250414035028.1561475-7-victor.liu@nxp.com
68 lines
1.8 KiB
YAML
68 lines
1.8 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-command-sequencer.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale i.MX8qxp Display Controller Command Sequencer
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description: |
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The Command Sequencer is designed to autonomously process command lists.
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By that it can load setups into the DC configuration and synchronize to
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hardware events. This releases a system's CPU from workload, because it
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does not need to wait for certain events. Also it simplifies SW architecture,
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because no interrupt handlers are required. Setups are read via AXI bus,
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while write access to configuration registers occurs directly via an internal
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bus. This saves bandwidth for the AXI interconnect and improves the system
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architecture in terms of safety aspects.
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maintainers:
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- Liu Ying <victor.liu@nxp.com>
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properties:
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compatible:
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const: fsl,imx8qxp-dc-command-sequencer
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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interrupts:
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maxItems: 5
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interrupt-names:
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items:
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- const: error
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- const: sw0
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- const: sw1
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- const: sw2
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- const: sw3
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sram:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: phandle pointing to the mmio-sram device node
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required:
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- compatible
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- reg
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- clocks
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- interrupts
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- interrupt-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/imx8-lpcg.h>
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command-sequencer@56180400 {
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compatible = "fsl,imx8qxp-dc-command-sequencer";
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reg = <0x56180400 0x1a4>;
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clocks = <&dc0_lpcg IMX_LPCG_CLK_5>;
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interrupt-parent = <&dc0_intc>;
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interrupts = <36>, <37>, <38>, <39>, <40>;
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interrupt-names = "error", "sw0", "sw1", "sw2", "sw3";
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};
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