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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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f85f2ce577
i.MX6SX has a single LVDS port and share a similar LDB_CTRL register layout with i.MX8MP and i.MX93. Signed-off-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Link: https://patchwork.freedesktop.org/patch/msgid/20230404020129.509356-1-festevam@gmail.com
123 lines
2.6 KiB
YAML
123 lines
2.6 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/bridge/fsl,ldb.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale i.MX8MP DPI to LVDS bridge chip
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maintainers:
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- Marek Vasut <marex@denx.de>
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description: |
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The i.MX8MP mediamix contains two registers which are responsible
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for configuring the on-SoC DPI-to-LVDS serializer. This describes
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those registers as bridge within the DT.
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properties:
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compatible:
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enum:
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- fsl,imx6sx-ldb
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- fsl,imx8mp-ldb
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- fsl,imx93-ldb
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clocks:
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maxItems: 1
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clock-names:
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const: ldb
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reg:
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maxItems: 2
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reg-names:
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items:
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- const: ldb
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- const: lvds
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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properties:
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port@0:
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$ref: /schemas/graph.yaml#/properties/port
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description: Video port for DPI input.
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port@1:
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$ref: /schemas/graph.yaml#/properties/port
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description: Video port for LVDS Channel-A output (panel or bridge).
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port@2:
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$ref: /schemas/graph.yaml#/properties/port
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description: Video port for LVDS Channel-B output (panel or bridge).
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required:
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- port@0
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- port@1
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required:
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- compatible
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- clocks
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- ports
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allOf:
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- if:
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properties:
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compatible:
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contains:
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enum:
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- fsl,imx6sx-ldb
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- fsl,imx93-ldb
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then:
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properties:
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ports:
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properties:
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port@2: false
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/imx8mp-clock.h>
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blk-ctrl {
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#address-cells = <1>;
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#size-cells = <1>;
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bridge@5c {
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compatible = "fsl,imx8mp-ldb";
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clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;
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clock-names = "ldb";
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reg = <0x5c 0x4>, <0x128 0x4>;
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reg-names = "ldb", "lvds";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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ldb_from_lcdif2: endpoint {
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remote-endpoint = <&lcdif2_to_ldb>;
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};
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};
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port@1 {
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reg = <1>;
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ldb_lvds_ch0: endpoint {
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remote-endpoint = <&ldb_to_lvdsx4panel>;
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};
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};
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port@2 {
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reg = <2>;
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ldb_lvds_ch1: endpoint {
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};
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};
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};
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};
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};
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