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63fd4d7dc4
Several TI SoC clock bindings were marked as work-in-progress / unstable
between 2013-2016, for example in commit f60b1ea5ea ("CLK: TI: add
support for gate clock"). It was enough of time to consider them stable
and expect usual ABI rules.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Tony Lindgren <tony@atomide.com>
Link: https://lore.kernel.org/r/20240224091236.10146-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Rob Herring <robh@kernel.org>
40 lines
1.3 KiB
Plaintext
40 lines
1.3 KiB
Plaintext
Binding for Texas Instruments ADPLL clock.
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This binding uses the common clock binding[1]. It assumes a
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register-mapped ADPLL with two to three selectable input clocks
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and three to four children.
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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Required properties:
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- compatible : shall be one of "ti,dm814-adpll-s-clock" or
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"ti,dm814-adpll-lj-clock" depending on the type of the ADPLL
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- #clock-cells : from common clock binding; shall be set to 1.
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- clocks : link phandles of parent clocks clkinp and clkinpulow, note
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that the adpll-s-clock also has an optional clkinphif
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- reg : address and length of the register set for controlling the ADPLL.
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Examples:
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adpll_mpu_ck: adpll@40 {
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#clock-cells = <1>;
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compatible = "ti,dm814-adpll-s-clock";
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reg = <0x40 0x40>;
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clocks = <&devosc_ck &devosc_ck &devosc_ck>;
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clock-names = "clkinp", "clkinpulow", "clkinphif";
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clock-output-names = "481c5040.adpll.dcoclkldo",
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"481c5040.adpll.clkout",
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"481c5040.adpll.clkoutx2",
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"481c5040.adpll.clkouthif";
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};
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adpll_dsp_ck: adpll@80 {
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#clock-cells = <1>;
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compatible = "ti,dm814-adpll-lj-clock";
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reg = <0x80 0x30>;
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clocks = <&devosc_ck &devosc_ck>;
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clock-names = "clkinp", "clkinpulow";
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clock-output-names = "481c5080.adpll.dcoclkldo",
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"481c5080.adpll.clkout",
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"481c5080.adpll.clkoutldo";
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};
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