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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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1b4bb451f3
Add device tree bindings for the TH1520 Video Output (VO) subsystem clock controller. The VO sub-system manages clock gates for multimedia components including HDMI, MIPI, and GPU. Document the VIDEO_PLL requirements for the VO clock controller, which receives its input from the AP clock controller. The VIDEO_PLL is a Silicon Creations Sigma-Delta (integer) PLL typically running at 792 MHz with maximum FOUTVCO of 2376 MHz. This binding complements the existing AP sub-system clock controller which manages CPU, DPU, GMAC and TEE PLLs. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com> Reviewed-by: Drew Fustini <drew@pdp7.com> Signed-off-by: Drew Fustini <drew@pdp7.com>
65 lines
1.8 KiB
YAML
65 lines
1.8 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/thead,th1520-clk-ap.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: T-HEAD TH1520 AP sub-system clock controller
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description: |
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The T-HEAD TH1520 AP sub-system clock controller configures the
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CPU, DPU, GMAC and TEE PLLs. Additionally the VO subsystem configures
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the clock gates for the HDMI, MIPI and the GPU.
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SoC reference manual
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https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/TH1520%20System%20User%20Manual.pdf
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maintainers:
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- Jisheng Zhang <jszhang@kernel.org>
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- Wei Fu <wefu@redhat.com>
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- Drew Fustini <dfustini@tenstorrent.com>
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properties:
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compatible:
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enum:
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- thead,th1520-clk-ap
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- thead,th1520-clk-vo
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reg:
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maxItems: 1
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clocks:
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items:
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- description: |
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One input clock:
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- For "thead,th1520-clk-ap": the clock input must be the 24 MHz
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main oscillator.
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- For "thead,th1520-clk-vo": the clock input must be the VIDEO_PLL,
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which is configured by the AP clock controller. According to the
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TH1520 manual, VIDEO_PLL is a Silicon Creations Sigma-Delta PLL
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(integer PLL) typically running at 792 MHz (FOUTPOSTDIV), with
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a maximum FOUTVCO of 2376 MHz.
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"#clock-cells":
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const: 1
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description:
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See <dt-bindings/clock/thead,th1520-clk-ap.h> for valid indices.
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required:
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- compatible
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- reg
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- clocks
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- "#clock-cells"
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/thead,th1520-clk-ap.h>
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clock-controller@ef010000 {
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compatible = "thead,th1520-clk-ap";
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reg = <0xef010000 0x1000>;
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clocks = <&osc>;
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#clock-cells = <1>;
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};
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