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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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1a21590498
The clock controller on the SG2044 provides common clock function for all IPs on the SoC. This device requires PLL clock to function normally. Add definition for the clock controller of the SG2044 SoC. Reviewed-by: Chen Wang <unicorn_wang@outlook.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250418020325.421257-4-inochiama@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
100 lines
2.5 KiB
YAML
100 lines
2.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/sophgo,sg2044-clk.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Sophgo SG2044 Clock Controller
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maintainers:
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- Inochi Amaoto <inochiama@gmail.com>
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description: |
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The Sophgo SG2044 clock controller requires an external oscillator
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as input clock.
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All available clocks are defined as preprocessor macros in
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include/dt-bindings/clock/sophgo,sg2044-clk.h
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properties:
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compatible:
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const: sophgo,sg2044-clk
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reg:
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maxItems: 1
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clocks:
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items:
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- description: fpll0
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- description: fpll1
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- description: fpll2
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- description: dpll0
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- description: dpll1
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- description: dpll2
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- description: dpll3
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- description: dpll4
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- description: dpll5
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- description: dpll6
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- description: dpll7
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- description: mpll0
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- description: mpll1
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- description: mpll2
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- description: mpll3
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- description: mpll4
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- description: mpll5
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clock-names:
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items:
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- const: fpll0
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- const: fpll1
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- const: fpll2
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- const: dpll0
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- const: dpll1
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- const: dpll2
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- const: dpll3
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- const: dpll4
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- const: dpll5
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- const: dpll6
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- const: dpll7
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- const: mpll0
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- const: mpll1
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- const: mpll2
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- const: mpll3
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- const: mpll4
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- const: mpll5
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'#clock-cells':
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- '#clock-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/sophgo,sg2044-pll.h>
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clock-controller@50002000 {
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compatible = "sophgo,sg2044-clk";
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reg = <0x50002000 0x1000>;
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#clock-cells = <1>;
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clocks = <&syscon CLK_FPLL0>, <&syscon CLK_FPLL1>,
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<&syscon CLK_FPLL2>, <&syscon CLK_DPLL0>,
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<&syscon CLK_DPLL1>, <&syscon CLK_DPLL2>,
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<&syscon CLK_DPLL3>, <&syscon CLK_DPLL4>,
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<&syscon CLK_DPLL5>, <&syscon CLK_DPLL6>,
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<&syscon CLK_DPLL7>, <&syscon CLK_MPLL0>,
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<&syscon CLK_MPLL1>, <&syscon CLK_MPLL2>,
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<&syscon CLK_MPLL3>, <&syscon CLK_MPLL4>,
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<&syscon CLK_MPLL5>;
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clock-names = "fpll0", "fpll1", "fpll2", "dpll0",
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"dpll1", "dpll2", "dpll3", "dpll4",
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"dpll5", "dpll6", "dpll7", "mpll0",
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"mpll1", "mpll2", "mpll3", "mpll4",
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"mpll5";
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};
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