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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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e0c0a97bc3
There are two types of clocks in RK3528 SoC, CRU-managed and SCMI-managed. Independent IDs are assigned to them. For the reset part, differing from previous Rockchip SoCs and downstream bindings which embeds register offsets into the IDs, gapless numbers starting from zero are used. Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250217061142.38480-6-ziyao@disroot.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
65 lines
1.5 KiB
YAML
65 lines
1.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/rockchip,rk3528-cru.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Rockchip RK3528 Clock and Reset Controller
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maintainers:
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- Yao Zi <ziyao@disroot.org>
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description: |
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The RK3528 clock controller generates the clock and also implements a reset
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controller for SoC peripherals. For example, it provides SCLK_UART0 and
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PCLK_UART0 as well as SRST_P_UART0 and SRST_S_UART0 for the first UART
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module.
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Each clock is assigned an identifier, consumer nodes can use it to specify
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the clock. All available clock and reset IDs are defined in dt-binding
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headers.
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properties:
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compatible:
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const: rockchip,rk3528-cru
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reg:
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maxItems: 1
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clocks:
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items:
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- description: External 24MHz oscillator clock
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- description: >
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50MHz clock generated by PHY module, for generating GMAC0 clocks only.
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clock-names:
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items:
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- const: xin24m
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- const: gmac0
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"#clock-cells":
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const: 1
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"#reset-cells":
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- "#clock-cells"
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- "#reset-cells"
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additionalProperties: false
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examples:
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- |
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clock-controller@ff4a0000 {
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compatible = "rockchip,rk3528-cru";
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reg = <0xff4a0000 0x30000>;
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clocks = <&xin24m>, <&gmac0_clk>;
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clock-names = "xin24m", "gmac0";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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