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c04269c022
Document the device tree bindings for the Renesas RZ/V2N (R9A09G056) SoC Clock Pulse Generator (CPG). Update `renesas,rzv2h-cpg.yaml` to include the compatible string for RZ/V2N SoC and adjust the title and description accordingly. Additionally, introduce `renesas,r9a09g056-cpg.h` to define core clock constants for the RZ/V2N SoC. Note the existing RZ/V2H(P) family-specific clock driver will be reused for this SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250407191628.323613-7-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
85 lines
2.4 KiB
YAML
85 lines
2.4 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas RZ/{G3E,V2H(P),V2N} Clock Pulse Generator (CPG)
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maintainers:
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- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
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description:
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On Renesas RZ/{G3E,V2H(P),V2N} SoCs, the CPG (Clock Pulse Generator) handles
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generation and control of clock signals for the IP modules, generation and
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control of resets, and control over booting, low power consumption and power
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supply domains.
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properties:
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compatible:
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enum:
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- renesas,r9a09g047-cpg # RZ/G3E
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- renesas,r9a09g056-cpg # RZ/V2N
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- renesas,r9a09g057-cpg # RZ/V2H
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reg:
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maxItems: 1
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clocks:
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items:
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- description: AUDIO_EXTAL clock input
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- description: RTXIN clock input
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- description: QEXTAL clock input
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clock-names:
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items:
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- const: audio_extal
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- const: rtxin
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- const: qextal
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'#clock-cells':
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description: |
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- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
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and a core clock reference, as defined in
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<dt-bindings/clock/renesas,r9a09g0*-cpg.h>,
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- For module clocks, the two clock specifier cells must be "CPG_MOD" and
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a module number. The module number is calculated as the CLKON register
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offset index multiplied by 16, plus the actual bit in the register
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used to turn the CLK ON. For example, for CGC_GIC_0_GICCLK, the
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calculation is (1 * 16 + 3) = 0x13.
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const: 2
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'#power-domain-cells':
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const: 0
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'#reset-cells':
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description:
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The single reset specifier cell must be the reset number. The reset number
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is calculated as the reset register offset index multiplied by 16, plus the
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actual bit in the register used to reset the specific IP block. For example,
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for SYS_0_PRESETN, the calculation is (3 * 16 + 0) = 0x30.
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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- '#power-domain-cells'
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- '#reset-cells'
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additionalProperties: false
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examples:
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- |
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clock-controller@10420000 {
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compatible = "renesas,r9a09g057-cpg";
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reg = <0x10420000 0x10000>;
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clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>;
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clock-names = "audio_extal", "rtxin", "qextal";
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#clock-cells = <2>;
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#power-domain-cells = <0>;
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#reset-cells = <1>;
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};
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