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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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4f1a62e2b3
Add bindings for the Qualcomm SM8750 Display Clock Controller (DISPCC). Bindings are similar to existing SM8550 and SM8650 (same clock inputs), but the clock hierarchy is quite different and these are not compatible devices. The binding header was copied from downstream sources, so I retained original copyrights. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250106-sm8750-dispcc-v2-1-6f42beda6317@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
102 lines
2.9 KiB
YAML
102 lines
2.9 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,sm8550-dispcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Display Clock & Reset Controller for SM8550
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maintainers:
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- Bjorn Andersson <andersson@kernel.org>
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- Neil Armstrong <neil.armstrong@linaro.org>
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description: |
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Qualcomm display clock control module provides the clocks, resets and power
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domains on SM8550, SM8650, SM8750 and few other platforms.
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See also:
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- include/dt-bindings/clock/qcom,sm8550-dispcc.h
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- include/dt-bindings/clock/qcom,sm8650-dispcc.h
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- include/dt-bindings/clock/qcom,sm8750-dispcc.h
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- include/dt-bindings/clock/qcom,x1e80100-dispcc.h
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properties:
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compatible:
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enum:
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- qcom,sar2130p-dispcc
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- qcom,sm8550-dispcc
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- qcom,sm8650-dispcc
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- qcom,sm8750-dispcc
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- qcom,x1e80100-dispcc
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clocks:
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items:
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- description: Board XO source
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- description: Board Always On XO source
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- description: Display's AHB clock
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- description: sleep clock
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- description: Byte clock from DSI PHY0
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- description: Pixel clock from DSI PHY0
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- description: Byte clock from DSI PHY1
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- description: Pixel clock from DSI PHY1
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- description: Link clock from DP PHY0
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- description: VCO DIV clock from DP PHY0
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- description: Link clock from DP PHY1
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- description: VCO DIV clock from DP PHY1
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- description: Link clock from DP PHY2
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- description: VCO DIV clock from DP PHY2
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- description: Link clock from DP PHY3
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- description: VCO DIV clock from DP PHY3
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power-domains:
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description:
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A phandle and PM domain specifier for the MMCX power domain.
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maxItems: 1
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required-opps:
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description:
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A phandle to an OPP node describing required MMCX performance point.
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maxItems: 1
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required:
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- compatible
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- clocks
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- '#power-domain-cells'
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allOf:
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- $ref: qcom,gcc.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,sm8550-gcc.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/power/qcom,rpmhpd.h>
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clock-controller@af00000 {
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compatible = "qcom,sm8550-dispcc";
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reg = <0x0af00000 0x10000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&rpmhcc RPMH_CXO_CLK_A>,
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<&gcc GCC_DISP_AHB_CLK>,
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<&sleep_clk>,
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<&dsi0_phy 0>,
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<&dsi0_phy 1>,
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<&dsi1_phy 0>,
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<&dsi1_phy 1>,
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<&dp0_phy 0>,
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<&dp0_phy 1>,
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<&dp1_phy 0>,
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<&dp1_phy 1>,
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<&dp2_phy 0>,
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<&dp2_phy 1>,
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<&dp3_phy 0>,
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<&dp3_phy 1>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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power-domains = <&rpmhpd RPMHPD_MMCX>;
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required-opps = <&rpmhpd_opp_low_svs>;
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};
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...
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