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3b4e2820e1
X1E80100 videocc is largely identical to SM8550, but needs slightly different PLL frequencies. Add a separate qcom,x1e80100-videocc compatible to the existing schema used for SM8550. Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org> Link: https://lore.kernel.org/r/20250709-x1e-videocc-v2-1-ad1acf5674b4@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
89 lines
2.2 KiB
YAML
89 lines
2.2 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,sm8450-videocc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Video Clock & Reset Controller on SM8450
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maintainers:
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- Taniya Das <quic_tdas@quicinc.com>
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- Jagadeesh Kona <quic_jkona@quicinc.com>
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description: |
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Qualcomm video clock control module provides the clocks, resets and power
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domains on SM8450.
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See also:
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include/dt-bindings/clock/qcom,sm8450-videocc.h
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include/dt-bindings/clock/qcom,sm8650-videocc.h
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properties:
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compatible:
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enum:
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- qcom,sm8450-videocc
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- qcom,sm8475-videocc
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- qcom,sm8550-videocc
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- qcom,sm8650-videocc
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- qcom,x1e80100-videocc
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clocks:
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items:
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- description: Board XO source
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- description: Video AHB clock from GCC
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power-domains:
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description:
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Power domains required for the clock controller to operate
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items:
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- description: MMCX power domain
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- description: MXC power domain
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required-opps:
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description:
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OPP nodes that describe required performance points on power domains
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items:
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- description: MMCX performance point
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- description: MXC performance point
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required:
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- compatible
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- clocks
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- power-domains
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- '#power-domain-cells'
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allOf:
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- $ref: qcom,gcc.yaml#
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,sm8450-videocc
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- qcom,sm8550-videocc
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then:
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required:
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- required-opps
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-sm8450.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/power/qcom,rpmhpd.h>
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videocc: clock-controller@aaf0000 {
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compatible = "qcom,sm8450-videocc";
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reg = <0x0aaf0000 0x10000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_VIDEO_AHB_CLK>;
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power-domains = <&rpmhpd RPMHPD_MMCX>,
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<&rpmhpd RPMHPD_MXC>;
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required-opps = <&rpmhpd_opp_low_svs>,
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<&rpmhpd_opp_low_svs>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...
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