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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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e51c16f9ee
No double colon is necessary in the description. Fix it for all bindings so future bindings won't have the same copy-paste mistake. Reported-by: Rob Herring <robh@kernel.org> Closes: https://lore.kernel.org/lkml/20250625150458.GA1182597-robh@kernel.org/ Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20250717-bindings-double-colon-v1-1-c04abc180fcd@fairphone.com Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
60 lines
1.3 KiB
YAML
60 lines
1.3 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,gcc-qcs404.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Global Clock & Reset Controller on QCS404
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maintainers:
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- Stephen Boyd <sboyd@kernel.org>
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- Taniya Das <quic_tdas@quicinc.com>
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description: |
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Qualcomm global clock control module provides the clocks, resets and power
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domains on QCS404.
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See also: include/dt-bindings/clock/qcom,gcc-qcs404.h
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properties:
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compatible:
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const: qcom,gcc-qcs404
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clocks:
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items:
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- description: XO source
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- description: Sleep clock source
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- description: PCIe 0 PIPE clock (optional)
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- description: DSI phy instance 0 dsi clock
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- description: DSI phy instance 0 byte clock
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- description: HDMI phy PLL clock
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clock-names:
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items:
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- const: cxo
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- const: sleep_clk
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- const: pcie_0_pipe_clk_src
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- const: dsi0pll
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- const: dsi0pllbyte
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- const: hdmi_pll
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required:
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- compatible
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- '#power-domain-cells'
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allOf:
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- $ref: qcom,gcc.yaml#
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unevaluatedProperties: false
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examples:
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- |
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clock-controller@1800000 {
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compatible = "qcom,gcc-qcs404";
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reg = <0x01800000 0x80000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...
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