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17a6d7cece
Convert lpc1850-cgu.txt to yaml format. Additional changes: - remove extra clock source nodes in example. - remove clock consumer in example. - remove clock-output-names and clock-clock-indices from required list to match existed dts. Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20250606162410.1361169-1-Frank.Li@nxp.com Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
100 lines
3.8 KiB
YAML
100 lines
3.8 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/nxp,lpc1850-cgu.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NXP LPC1850 Clock Generation Unit (CGU)
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description: >
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The CGU generates multiple independent clocks for the core and the
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peripheral blocks of the LPC18xx. Each independent clock is called
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a base clock and itself is one of the inputs to the two Clock
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Control Units (CCUs) which control the branch clocks to the
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individual peripherals.
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The CGU selects the inputs to the clock generators from multiple
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clock sources, controls the clock generation, and routes the outputs
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of the clock generators through the clock source bus to the output
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stages. Each output stage provides an independent clock source and
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corresponds to one of the base clocks for the LPC18xx.
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Above text taken from NXP LPC1850 User Manual.
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maintainers:
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- Frank Li <Frank.Li@nxp.com>
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properties:
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compatible:
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const: nxp,lpc1850-cgu
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reg:
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maxItems: 1
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'#clock-cells':
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const: 1
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description: |
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Which base clocks that are available on the CGU depends on the
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specific LPC part. Base clocks are numbered from 0 to 27.
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Number: Name: Description:
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0 BASE_SAFE_CLK Base safe clock (always on) for WWDT
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1 BASE_USB0_CLK Base clock for USB0
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2 BASE_PERIPH_CLK Base clock for Cortex-M0SUB subsystem,
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SPI, and SGPIO
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3 BASE_USB1_CLK Base clock for USB1
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4 BASE_CPU_CLK System base clock for ARM Cortex-M core
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and APB peripheral blocks #0 and #2
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5 BASE_SPIFI_CLK Base clock for SPIFI
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6 BASE_SPI_CLK Base clock for SPI
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7 BASE_PHY_RX_CLK Base clock for Ethernet PHY Receive clock
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8 BASE_PHY_TX_CLK Base clock for Ethernet PHY Transmit clock
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9 BASE_APB1_CLK Base clock for APB peripheral block # 1
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10 BASE_APB3_CLK Base clock for APB peripheral block # 3
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11 BASE_LCD_CLK Base clock for LCD
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12 BASE_ADCHS_CLK Base clock for ADCHS
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13 BASE_SDIO_CLK Base clock for SD/MMC
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14 BASE_SSP0_CLK Base clock for SSP0
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15 BASE_SSP1_CLK Base clock for SSP1
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16 BASE_UART0_CLK Base clock for UART0
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17 BASE_UART1_CLK Base clock for UART1
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18 BASE_UART2_CLK Base clock for UART2
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19 BASE_UART3_CLK Base clock for UART3
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20 BASE_OUT_CLK Base clock for CLKOUT pin
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24-21 - Reserved
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25 BASE_AUDIO_CLK Base clock for audio system (I2S)
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26 BASE_CGU_OUT0_CLK Base clock for CGU_OUT0 clock output
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27 BASE_CGU_OUT1_CLK Base clock for CGU_OUT1 clock output
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BASE_PERIPH_CLK and BASE_SPI_CLK is only available on LPC43xx.
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BASE_ADCHS_CLK is only available on LPC4370.
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clocks:
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maxItems: 5
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clock-indices:
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minItems: 1
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maxItems: 28
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clock-output-names:
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minItems: 1
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maxItems: 28
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required:
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- compatible
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- reg
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- clocks
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- '#clock-cells'
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additionalProperties: false
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examples:
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- |
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clock-controller@40050000 {
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compatible = "nxp,lpc1850-cgu";
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reg = <0x40050000 0x1000>;
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#clock-cells = <1>;
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clocks = <&xtal>, <&creg_clk 1>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>;
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};
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