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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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e3fcba910a
Convert the Marvell Dove PLL divider clock binding to DT schema format. It's a straight forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250521210832.62177-1-robh@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
51 lines
1.0 KiB
YAML
51 lines
1.0 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/marvell,dove-divider-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Marvell Dove PLL Divider Clock
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maintainers:
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- Andrew Lunn <andrew@lunn.ch>
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- Gregory Clement <gregory.clement@bootlin.com>
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description: >
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Marvell Dove has a 2GHz PLL, which feeds into a set of dividers to provide
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high speed clocks for a number of peripherals. These dividers are part of the
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PMU, and thus this node should be a child of the PMU node.
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The following clocks are provided:
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ID Clock
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-------------
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0 AXI bus clock
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1 GPU clock
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2 VMeta clock
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3 LCD clock
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properties:
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compatible:
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const: marvell,dove-divider-clock
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reg:
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maxItems: 1
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'#clock-cells':
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const: 1
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required:
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- compatible
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- reg
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- '#clock-cells'
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additionalProperties: false
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examples:
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- |
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clock-controller@64 {
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compatible = "marvell,dove-divider-clock";
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reg = <0x0064 0x8>;
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#clock-cells = <1>;
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};
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