mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-09-03 17:51:23 +00:00

Convert the Marvell Armada 3700 peripheral clock binding to DT schema format. The north bridge is also a "syscon", so add the compatible to it. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250521211826.77098-1-robh@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
97 lines
2.7 KiB
YAML
97 lines
2.7 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
|
%YAML 1.2
|
|
---
|
|
$id: http://devicetree.org/schemas/clock/marvell,armada-3700-periph-clock.yaml#
|
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
|
|
|
title: Marvell Armada 37xx SoCs Peripheral Clocks
|
|
|
|
maintainers:
|
|
- Andrew Lunn <andrew@lunn.ch>
|
|
- Gregory Clement <gregory.clement@bootlin.com>
|
|
|
|
description: >
|
|
Marvell Armada 37xx SoCs provide peripheral clocks which are used as clock
|
|
source for the peripheral of the SoC.
|
|
|
|
There are two different blocks associated to north bridge and south bridge.
|
|
|
|
The following is a list of provided IDs for Armada 3700 North bridge clocks:
|
|
|
|
ID Clock name Description
|
|
-----------------------------------
|
|
0 mmc MMC controller
|
|
1 sata_host Sata Host
|
|
2 sec_at Security AT
|
|
3 sac_dap Security DAP
|
|
4 tsecm Security Engine
|
|
5 setm_tmx Serial Embedded Trace Module
|
|
6 avs Adaptive Voltage Scaling
|
|
7 sqf SPI
|
|
8 pwm PWM
|
|
9 i2c_2 I2C 2
|
|
10 i2c_1 I2C 1
|
|
11 ddr_phy DDR PHY
|
|
12 ddr_fclk DDR F clock
|
|
13 trace Trace
|
|
14 counter Counter
|
|
15 eip97 EIP 97
|
|
16 cpu CPU
|
|
|
|
The following is a list of provided IDs for Armada 3700 South bridge clocks:
|
|
|
|
ID Clock name Description
|
|
-----------------------------------
|
|
0 gbe-50 50 MHz parent clock for Gigabit Ethernet
|
|
1 gbe-core parent clock for Gigabit Ethernet core
|
|
2 gbe-125 125 MHz parent clock for Gigabit Ethernet
|
|
3 gbe1-50 50 MHz clock for Gigabit Ethernet port 1
|
|
4 gbe0-50 50 MHz clock for Gigabit Ethernet port 0
|
|
5 gbe1-125 125 MHz clock for Gigabit Ethernet port 1
|
|
6 gbe0-125 125 MHz clock for Gigabit Ethernet port 0
|
|
7 gbe1-core Gigabit Ethernet core port 1
|
|
8 gbe0-core Gigabit Ethernet core port 0
|
|
9 gbe-bm Gigabit Ethernet Buffer Manager
|
|
10 sdio SDIO
|
|
11 usb32-sub2-sys USB 2 clock
|
|
12 usb32-ss-sys USB 3 clock
|
|
13 pcie PCIe controller
|
|
|
|
properties:
|
|
compatible:
|
|
oneOf:
|
|
- const: marvell,armada-3700-periph-clock-sb
|
|
- items:
|
|
- const: marvell,armada-3700-periph-clock-nb
|
|
- const: syscon
|
|
reg:
|
|
maxItems: 1
|
|
|
|
clocks:
|
|
items:
|
|
- description: TBG-A P clock and specifier
|
|
- description: TBG-B P clock and specifier
|
|
- description: TBG-A S clock and specifier
|
|
- description: TBG-B S clock and specifier
|
|
- description: Xtal clock and specifier
|
|
|
|
'#clock-cells':
|
|
const: 1
|
|
|
|
required:
|
|
- compatible
|
|
- reg
|
|
- clocks
|
|
- '#clock-cells'
|
|
|
|
additionalProperties: false
|
|
|
|
examples:
|
|
- |
|
|
clock-controller@13000{
|
|
compatible = "marvell,armada-3700-periph-clock-sb";
|
|
reg = <0x13000 0x1000>;
|
|
clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, <&tbg 3>, <&xtalclk>;
|
|
#clock-cells = <1>;
|
|
};
|