mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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47f3f5a82a
In order to access the registers of the HW, we need to make sure that
the AXI bus clock is enabled. Hence let's increase the number of clocks
by one and add clock-names to differentiate between parent clocks and
the bus clock.
Fixes: 0e646c52cf ("clk: Add axi-clkgen driver")
Signed-off-by: Nuno Sa <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20241029-axi-clkgen-fix-axiclk-v2-1-bc5e0733ad76@analog.com
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
69 lines
1.6 KiB
YAML
69 lines
1.6 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/adi,axi-clkgen.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Analog Devices AXI clkgen pcore clock generator
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maintainers:
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- Lars-Peter Clausen <lars@metafoo.de>
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- Michael Hennerich <michael.hennerich@analog.com>
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description: |
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The axi_clkgen IP core is a software programmable clock generator,
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that can be synthesized on various FPGA platforms.
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Link: https://wiki.analog.com/resources/fpga/docs/axi_clkgen
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properties:
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compatible:
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enum:
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- adi,axi-clkgen-2.00.a
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- adi,zynqmp-axi-clkgen-2.00.a
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clocks:
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description:
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Specifies the reference clock(s) from which the output frequency is
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derived. This must either reference one clock if only the first clock
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input is connected or two if both clock inputs are connected. The last
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clock is the AXI bus clock that needs to be enabled so we can access the
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core registers.
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minItems: 2
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maxItems: 3
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clock-names:
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oneOf:
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- items:
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- const: clkin1
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- const: s_axi_aclk
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- items:
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- const: clkin1
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- const: clkin2
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- const: s_axi_aclk
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'#clock-cells':
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const: 0
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reg:
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maxItems: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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additionalProperties: false
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examples:
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- |
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clock-controller@ff000000 {
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compatible = "adi,axi-clkgen-2.00.a";
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#clock-cells = <0>;
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reg = <0xff000000 0x1000>;
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clocks = <&osc 1>, <&clkc 15>;
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clock-names = "clkin1", "s_axi_aclk";
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};
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