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51b081cdb9
Add a new compatible string for ax45mp-cache on QiLai SoC. Also, add allOf constraints to enforce specific cache-sets and cache-size values for qilai-ax45mp-cache. Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
100 lines
2.0 KiB
YAML
100 lines
2.0 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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# Copyright (C) 2023 Renesas Electronics Corp.
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/cache/andestech,ax45mp-cache.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Andestech AX45MP L2 Cache Controller
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maintainers:
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- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
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description:
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A level-2 cache (L2C) is used to improve the system performance by providing
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a large amount of cache line entries and reasonable access delays. The L2C
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is shared between cores, and a non-inclusive non-exclusive policy is used.
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select:
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properties:
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compatible:
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contains:
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enum:
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- andestech,ax45mp-cache
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required:
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- compatible
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properties:
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compatible:
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items:
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- enum:
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- andestech,qilai-ax45mp-cache
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- renesas,r9a07g043f-ax45mp-cache
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- const: andestech,ax45mp-cache
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- const: cache
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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cache-line-size:
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const: 64
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cache-level:
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const: 2
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cache-sets:
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const: 1024
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cache-size:
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enum: [131072, 262144, 524288, 1048576, 2097152]
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cache-unified: true
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next-level-cache: true
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additionalProperties: false
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required:
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- compatible
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- reg
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- interrupts
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- cache-line-size
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- cache-level
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- cache-sets
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- cache-size
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- cache-unified
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: andestech,qilai-ax45mp-cache
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then:
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properties:
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cache-sets:
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const: 2048
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cache-size:
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const: 2097152
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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cache-controller@13400000 {
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compatible = "renesas,r9a07g043f-ax45mp-cache", "andestech,ax45mp-cache",
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"cache";
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reg = <0x13400000 0x100000>;
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interrupts = <508 IRQ_TYPE_LEVEL_HIGH>;
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cache-line-size = <64>;
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cache-level = <2>;
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cache-sets = <1024>;
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cache-size = <262144>;
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cache-unified;
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};
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