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6865c64541
commitb0a5cde57c("dt-bindings: mfd: Explain lack of child dependency in simple-mfd") pointed out that it's a mistake for a child device of a simple MFD device to depend on the simple MFD device's clock resources. fsl,imx8qxp-csr.yaml happens to make that mistake. To fix that, remove fsl,imx8qxp-csr.yaml and use "simple-pm-bus" and "syscon" as the CSR node's compatible strings in the examples of fsl,imx8qxp-pixel-link-msi-bus.yaml to replace the wrong compatible strings which include "simple-mfd" and "fsl,imx8qxp-mipi-lvds-csr". Since fsl,imx8qxp-pixel-link-msi-bus.yaml as the last user of the CSR compatible strings no longer uses them, it's safe to remove the fsl,imx8qxp-csr.yaml binding documentation. Fixes:9b2c55b540("dt-bindings: mfd: Add i.MX8qm/qxp Control and Status Registers module binding") Fixes:c08645ea21("dt-bindings: bus: Add Freescale i.MX8qxp pixel link MSI bus binding") Signed-off-by: Liu Ying <victor.liu@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20250620022537.3072877-1-victor.liu@nxp.com Signed-off-by: Lee Jones <lee@kernel.org>
233 lines
7.3 KiB
YAML
233 lines
7.3 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale i.MX8qxp Pixel Link Medium Speed Interconnect (MSI) Bus
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maintainers:
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- Liu Ying <victor.liu@nxp.com>
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description: |
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i.MX8qxp pixel link MSI bus is used to control settings of PHYs, I/Os
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sitting together with the PHYs. It is not the same as the MSI bus coming
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from i.MX8 System Controller Unit (SCU) which is used to control power,
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clock and reset through the i.MX8 Distributed Slave System Controller (DSC).
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i.MX8qxp pixel link MSI bus is a simple memory-mapped bus. Two input clocks,
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that is, MSI clock and AHB clock, need to be enabled so that peripherals
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connected to the bus can be accessed. Also, the bus is part of a power
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domain. The power domain needs to be enabled before the peripherals can
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be accessed.
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Peripherals in i.MX8qm/qxp imaging, LVDS, MIPI DSI and HDMI TX subsystems,
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like I2C controller, PWM controller, MIPI DSI controller and Control and
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Status Registers (CSR) module, are accessed through the bus.
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The i.MX System Controller Firmware (SCFW) owns and uses the i.MX8qm/qxp
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pixel link MSI bus controller and does not allow SCFW user to control it.
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So, the controller's registers cannot be accessed by SCFW user. Hence,
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the interrupts generated by the controller don't make any sense from SCFW
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user's point of view.
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allOf:
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- $ref: simple-pm-bus.yaml#
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# We need a select here so we don't match all nodes with 'simple-pm-bus'.
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select:
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properties:
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compatible:
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contains:
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enum:
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- fsl,imx8qxp-display-pixel-link-msi-bus
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- fsl,imx8qm-display-pixel-link-msi-bus
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required:
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- compatible
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properties:
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compatible:
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items:
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- enum:
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- fsl,imx8qxp-display-pixel-link-msi-bus
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- fsl,imx8qm-display-pixel-link-msi-bus
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- const: simple-pm-bus
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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items:
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- description: master gated clock from system
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- description: AHB clock
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clock-names:
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items:
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- const: msi
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- const: ahb
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patternProperties:
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"^.*@[0-9a-f]+$":
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description: Devices attached to the bus
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type: object
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required:
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- reg
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- power-domains
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/imx8-lpcg.h>
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#include <dt-bindings/firmware/imx/rsrc.h>
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bus@56200000 {
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compatible = "fsl,imx8qxp-display-pixel-link-msi-bus", "simple-pm-bus";
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reg = <0x56200000 0x20000>;
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&dc0_irqsteer>;
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interrupts = <320>;
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ranges;
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clocks = <&dc0_disp_ctrl_link_mst0_lpcg IMX_LPCG_CLK_4>,
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<&dc0_disp_ctrl_link_mst0_lpcg IMX_LPCG_CLK_4>;
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clock-names = "msi", "ahb";
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power-domains = <&pd IMX_SC_R_DC_0>;
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bus@56221000 {
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compatible = "simple-pm-bus", "syscon";
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reg = <0x56221000 0x1000>;
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clocks = <&mipi_lvds_0_di_mipi_lvds_regs_lpcg IMX_LPCG_CLK_4>;
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clock-names = "ipg";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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pxl2dpi {
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compatible = "fsl,imx8qxp-pxl2dpi";
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fsl,sc-resource = <IMX_SC_R_MIPI_0>;
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power-domains = <&pd IMX_SC_R_MIPI_0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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mipi_lvds_0_pxl2dpi_dc0_pixel_link0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&dc0_pixel_link0_mipi_lvds_0_pxl2dpi>;
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};
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mipi_lvds_0_pxl2dpi_dc0_pixel_link1: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&dc0_pixel_link1_mipi_lvds_0_pxl2dpi>;
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};
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};
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port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi>;
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};
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mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi>;
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};
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};
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};
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};
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ldb {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx8qxp-ldb";
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clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>,
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<&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>;
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clock-names = "pixel", "bypass";
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power-domains = <&pd IMX_SC_R_LVDS_0>;
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channel@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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phys = <&mipi_lvds_0_phy>;
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phy-names = "lvds_phy";
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port@0 {
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reg = <0>;
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mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi: endpoint {
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remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0>;
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};
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};
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port@1 {
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reg = <1>;
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/* ... */
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};
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};
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channel@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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phys = <&mipi_lvds_0_phy>;
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phy-names = "lvds_phy";
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port@0 {
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reg = <0>;
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mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi: endpoint {
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remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1>;
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};
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};
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port@1 {
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reg = <1>;
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/* ... */
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};
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};
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};
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};
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clock-controller@56223004 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x56223004 0x4>;
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#clock-cells = <1>;
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clocks = <&mipi_lvds_0_ipg_clk>;
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clock-indices = <IMX_LPCG_CLK_4>;
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clock-output-names = "mipi_lvds_0_di_mipi_lvds_regs_lpcg_ipg_clk";
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power-domains = <&pd IMX_SC_R_MIPI_0>;
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};
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phy@56228300 {
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compatible = "fsl,imx8qxp-mipi-dphy";
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reg = <0x56228300 0x100>;
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clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_PHY>;
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clock-names = "phy_ref";
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#phy-cells = <0>;
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fsl,syscon = <&mipi_lvds_0_csr>;
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power-domains = <&pd IMX_SC_R_MIPI_0>;
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};
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};
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