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5ff80684fb
Add i.MX8QM AHCI "fsl,imx8qm-ahci" compatible strings. i.MX8QM AHCI SATA doesn't require AHB clock rate to set the vendor specified TIMER1MS register. ahb clock is not required by i.MX8QM AHCI. Update the description of clocks in the dt-binding accordingly. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/1723428055-27021-2-git-send-email-hongxing.zhu@nxp.com Signed-off-by: Niklas Cassel <cassel@kernel.org>
131 lines
3.1 KiB
YAML
131 lines
3.1 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/ata/imx-sata.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale i.MX AHCI SATA Controller
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maintainers:
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- Shawn Guo <shawn.guo@linaro.org>
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description: |
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The Freescale i.MX SATA controller mostly conforms to the AHCI interface
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with some special extensions at integration level.
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properties:
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compatible:
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enum:
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- fsl,imx53-ahci
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- fsl,imx6q-ahci
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- fsl,imx6qp-ahci
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- fsl,imx8qm-ahci
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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minItems: 2
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items:
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- description: sata clock
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- description: sata reference clock
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- description: ahb clock
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clock-names:
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minItems: 2
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items:
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- const: sata
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- const: sata_ref
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- const: ahb
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fsl,transmit-level-mV:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: transmit voltage level, in millivolts.
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fsl,transmit-boost-mdB:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: transmit boost level, in milli-decibels.
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fsl,transmit-atten-16ths:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: transmit attenuation, in 16ths.
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fsl,receive-eq-mdB:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: receive equalisation, in milli-decibels.
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fsl,no-spread-spectrum:
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$ref: /schemas/types.yaml#/definitions/flag
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description: if present, disable spread-spectrum clocking on the SATA link.
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phys:
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items:
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- description: phandle to SATA PHY.
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Since "REXT" pin is only present for first lane of i.MX8QM PHY, it's
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calibration result will be stored, passed through second lane, and
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shared with all three lanes PHY. The first two lanes PHY are used as
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calibration PHYs, although only the third lane PHY is used by SATA.
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- description: phandle to the first lane PHY of i.MX8QM.
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- description: phandle to the second lane PHY of i.MX8QM.
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phy-names:
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items:
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- const: sata-phy
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- const: cali-phy0
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- const: cali-phy1
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power-domains:
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maxItems: 1
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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allOf:
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- if:
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properties:
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compatible:
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contains:
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enum:
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- fsl,imx53-ahci
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- fsl,imx6q-ahci
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- fsl,imx6qp-ahci
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then:
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properties:
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clock-names:
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minItems: 3
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- if:
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properties:
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compatible:
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contains:
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enum:
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- fsl,imx8qm-ahci
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then:
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properties:
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clock-names:
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minItems: 2
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/imx6qdl-clock.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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sata@2200000 {
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compatible = "fsl,imx6q-ahci";
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reg = <0x02200000 0x4000>;
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interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6QDL_CLK_SATA>,
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<&clks IMX6QDL_CLK_SATA_REF_100M>,
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<&clks IMX6QDL_CLK_AHB>;
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clock-names = "sata", "sata_ref", "ahb";
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};
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