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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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064f14e9df
Baikal-T1 AHCI controller is based on the DWC AHCI SATA IP-core v4.10a with the next specific settings: two SATA ports, cascaded CSR access based on two clock domains (APB and AXI), selectable source of the reference clock (though stable work is currently available from the external source only), two reset lanes for the application and SATA ports domains. Other than that the device is fully compatible with the generic DWC AHCI SATA bindings. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Reviewed-by: Hannes Reinecke <hare@suse.de> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
116 lines
2.4 KiB
YAML
116 lines
2.4 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/ata/baikal,bt1-ahci.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Baikal-T1 SoC AHCI SATA controller
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maintainers:
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- Serge Semin <fancer.lancer@gmail.com>
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description:
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AHCI SATA controller embedded into the Baikal-T1 SoC is based on the
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DWC AHCI SATA v4.10a IP-core.
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allOf:
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- $ref: snps,dwc-ahci-common.yaml#
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properties:
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compatible:
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const: baikal,bt1-ahci
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clocks:
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items:
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- description: Peripheral APB bus clock
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- description: Application AXI BIU clock
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- description: SATA Ports reference clock
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clock-names:
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items:
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- const: pclk
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- const: aclk
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- const: ref
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resets:
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items:
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- description: Application AXI BIU domain reset
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- description: SATA Ports clock domain reset
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reset-names:
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items:
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- const: arst
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- const: ref
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ports-implemented:
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maximum: 0x3
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patternProperties:
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"^sata-port@[0-1]$":
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$ref: /schemas/ata/snps,dwc-ahci-common.yaml#/$defs/dwc-ahci-port
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properties:
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reg:
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minimum: 0
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maximum: 1
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snps,tx-ts-max:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Due to having AXI3 bus interface utilized the maximum Tx DMA
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transaction size can't exceed 16 beats (AxLEN[3:0]).
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enum: [ 1, 2, 4, 8, 16 ]
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snps,rx-ts-max:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Due to having AXI3 bus interface utilized the maximum Rx DMA
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transaction size can't exceed 16 beats (AxLEN[3:0]).
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enum: [ 1, 2, 4, 8, 16 ]
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unevaluatedProperties: false
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- resets
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unevaluatedProperties: false
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examples:
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- |
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sata@1f050000 {
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compatible = "baikal,bt1-ahci";
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reg = <0x1f050000 0x2000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 64 4>;
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clocks = <&ccu_sys 1>, <&ccu_axi 2>, <&sata_ref_clk>;
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clock-names = "pclk", "aclk", "ref";
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resets = <&ccu_axi 2>, <&ccu_sys 0>;
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reset-names = "arst", "ref";
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ports-implemented = <0x3>;
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sata-port@0 {
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reg = <0>;
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snps,tx-ts-max = <4>;
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snps,rx-ts-max = <4>;
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};
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sata-port@1 {
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reg = <1>;
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snps,tx-ts-max = <4>;
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snps,rx-ts-max = <4>;
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};
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};
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...
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