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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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24822c4b47
Convert the clock device tree bindings to yaml for the Altera SoCFPGA Cyclone5, Arria5, and Arria10 chip families. Since the clock nodes are subnodes to Altera SOCFPGA Clock Manager, the yaml was added to socfpga-clk-manager.yaml. Signed-off-by: Matthew Gerlach <matthew.gerlach@altera.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
134 lines
2.9 KiB
YAML
134 lines
2.9 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/altera/socfpga-clk-manager.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Altera SOCFPGA Clock Manager
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maintainers:
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- Dinh Nguyen <dinguyen@kernel.org>
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description:
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This binding describes the Altera SOCFGPA Clock Manager and its associated
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tree of clocks, pll's, and clock gates for the Cyclone5, Arria5 and Arria10
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chip families.
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properties:
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compatible:
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items:
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- const: altr,clk-mgr
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reg:
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maxItems: 1
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clocks:
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type: object
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additionalProperties: false
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properties:
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"#address-cells":
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const: 1
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"#size-cells":
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const: 0
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patternProperties:
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"^osc[0-9]$":
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type: object
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"^[a-z0-9,_]+(clk|pll|clk_gate|clk_divided)(@[a-f0-9]+)?$":
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type: object
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$ref: '#/$defs/clock-props'
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unevaluatedProperties: false
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properties:
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compatible:
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enum:
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- altr,socfpga-pll-clock
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- altr,socfpga-perip-clk
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- altr,socfpga-gate-clk
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- altr,socfpga-a10-pll-clock
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- altr,socfpga-a10-perip-clk
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- altr,socfpga-a10-gate-clk
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- fixed-clock
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clocks:
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description: one or more phandles to input clock
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minItems: 1
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maxItems: 5
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"#address-cells":
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const: 1
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"#size-cells":
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const: 0
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patternProperties:
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"^[a-z0-9,_]+(clk|pll)(@[a-f0-9]+)?$":
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type: object
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$ref: '#/$defs/clock-props'
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unevaluatedProperties: false
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properties:
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compatible:
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enum:
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- altr,socfpga-perip-clk
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- altr,socfpga-gate-clk
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- altr,socfpga-a10-perip-clk
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- altr,socfpga-a10-gate-clk
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clocks:
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description: one or more phandles to input clock
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minItems: 1
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maxItems: 4
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required:
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- compatible
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- clocks
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- "#clock-cells"
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required:
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- compatible
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- "#clock-cells"
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required:
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- compatible
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- reg
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additionalProperties: false
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$defs:
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clock-props:
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properties:
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reg:
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maxItems: 1
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"#clock-cells":
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const: 0
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clk-gate:
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$ref: /schemas/types.yaml#/definitions/uint32-array
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items:
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- description: gating register offset
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- description: bit index
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div-reg:
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$ref: /schemas/types.yaml#/definitions/uint32-array
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items:
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- description: divider register offset
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- description: bit shift
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- description: bit width
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fixed-divider:
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$ref: /schemas/types.yaml#/definitions/uint32
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examples:
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- |
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clkmgr@ffd04000 {
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compatible = "altr,clk-mgr";
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reg = <0xffd04000 0x1000>;
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};
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...
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