/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */

#ifndef _DT_BINDINGS_MEDIATEK_MT6363_AUXADC_H
#define _DT_BINDINGS_MEDIATEK_MT6363_AUXADC_H

/* ADC Channel Index */
#define MT6363_AUXADC_BATADC		0
#define MT6363_AUXADC_VCDT		1
#define MT6363_AUXADC_BAT_TEMP		2
#define MT6363_AUXADC_CHIP_TEMP		3
#define MT6363_AUXADC_VSYSSNS		4
#define MT6363_AUXADC_VTREF		5
#define MT6363_AUXADC_VCORE_TEMP	6
#define MT6363_AUXADC_VPROC_TEMP	7
#define MT6363_AUXADC_VGPU_TEMP		8
#define MT6363_AUXADC_VIN1		9
#define MT6363_AUXADC_VIN2		10
#define MT6363_AUXADC_VIN3		11
#define MT6363_AUXADC_VIN4		12
#define MT6363_AUXADC_VIN5		13
#define MT6363_AUXADC_VIN6		14
#define MT6363_AUXADC_VIN7		15

#endif