4 Commits

Author	SHA1	Message	Date
Keith Packard	fb0f8fbf97	drm/i915: Generate 2MHz clock for display port aux channel I/O. Retry I/O. ... The display port aux channel clock is taken from the hrawclk value, which is provided to the chip as the FSB frequency (as far as I can determine). The strapping values for that are available in the CLKCFG register, now used to select an appropriate divider to generate a 2MHz clock. In addition, the DisplayPort spec requires that each aux channel I/O be retried 'at least 3 times' in case the sink is idle when the first request comes in. Signed-off-by: Keith Packard <keithp@keithp.com>	2009-06-18 15:54:14 -07:00
Keith Packard	a5b3da543d	drm/i915: Clarify error returns from display port aux channel I/O ... Use distinct error return values for each kind of aux channel I/O failure. Signed-off-by: Keith Packard <keithp@keithp.com>	2009-06-18 15:54:12 -07:00
Keith Packard	c8110e52b7	drm/i915: Use hotplug callback to retrain DP link ... When a DP monitor is plugged back in, it needs to be retrained if it was active before. Signed-off-by: Keith Packard <keithp@keithp.com>	2009-06-18 15:54:08 -07:00
Keith Packard	a4fc5ed698	drm/i915: Add Display Port support ... Signed-off-by: Keith Packard <keithp@keithp.com>	2009-06-18 15:54:07 -07:00