Overhaul the riscv vector tests to use kselftest_harness to help the
test cases correctly report the results and decouple the individual test
cases from each other. With this refactoring, only run the test cases if
vector is reported and properly report the test case as skipped
otherwise. The v_initval_nolibc test was previously not checking if
vector was supported and used a function (malloc) which invalidates
the state of the vector registers.
Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
Tested-by: Yangyu Chen <cyy@cyyself.name>
Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-12-236c22791ef9@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
This add a test to check if the kernel zero-initializes all V registers
after the first-use trap handler returns.
If V registers are not zero-initialized, then the test should fail one
out of several runs:
```
root@sifive-fpga:~# ./v_initval_nolibc
# vl = 256
not ok 1 detect stale values on v-regesters
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 4c 41 4e 47 3d 43 0 50 41 54 48 3d 2f 75 73
72 2f 6c 6f 63 61 6c 2f 73 62 69 6e 3a 2f 75 73
72 2f 6c 6f 63 61 6c 2f 62 69 6e 3a 2f 75 73 72
ff ff 81 0 0 0 0 0 0 0 0 0 0 0 0 0
```
Otherwise, the test passes without errors each run.
Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
Reviewed-by: Björn Töpel <bjorn@rivosinc.com>
Link: https://lore.kernel.org/r/20230627015556.12329-3-andy.chiu@sifive.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
