mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-09-03 17:51:23 +00:00
loongarch-next
326 Commits
| Author | SHA1 | Message | Date | |
|---|---|---|---|---|
Mikko Perttunen
|
0e2b014eeb |
dt-bindings: Add headers for NVDEC on Tegra234
Add clock, memory controller, powergate and reset dt-binding headers necessary for NVDEC. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com> |
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Stephen Boyd
|
f9efefdba9 |
Merge branches 'clk-baikal', 'clk-broadcom', 'clk-vc5' and 'clk-versaclock' into clk-next
- Convert Baikal-T1 CCU driver to platform driver
- Split reset support out of primary Baikal-T1 CCU driver
- Add some missing clks required for RPiVid Video Decoder on RaspberryPi
- Mark PLLC critical on bcm2835
- Support for Renesas VersaClock7 clock generator family
* clk-baikal:
clk: baikal-t1: Convert to platform device driver
clk: baikal-t1: Add DDR/PCIe directly controlled resets support
dt-bindings: clk: baikal-t1: Add DDR/PCIe reset IDs
clk: baikal-t1: Move reset-controls code into a dedicated module
clk: baikal-t1: Add SATA internal ref clock buffer
clk: baikal-t1: Add shared xGMAC ref/ptp clocks internal parent
clk: baikal-t1: Fix invalid xGMAC PTP clock divider
clk: vc5: Fix 5P49V6901 outputs disabling when enabling FOD
* clk-broadcom:
clk: bcm: rpi: Add support for VEC clock
clk: bcm: rpi: Handle pixel clock in firmware
clk: bcm: rpi: Add support HEVC clock
clk: bcm2835: fix bcm2835_clock_rate_from_divisor declaration
clk: bcm2835: Round UART input clock up
clk: bcm2835: Make peripheral PLLC critical
* clk-vc5:
clk: vc5: Add support for IDT/Renesas VersaClock 5P49V6975
dt-bindings: clock: vc5: Add 5P49V6975
clk: vc5: Use regmap_{set,clear}_bits() where appropriate
clk: vc5: Check IO access results
* clk-versaclock:
clk: Renesas versaclock7 ccf device driver
dt-bindings: Renesas versaclock7 device tree bindings
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Serge Semin
|
c0cd3b1790 |
dt-bindings: clk: baikal-t1: Add DDR/PCIe reset IDs
Aside with a set of the trigger-like resets Baikal-T1 CCU provides additional directly controlled reset signals for the DDR and PCIe controllers. As a preparation before adding these resets support to the kernel let's extent the Baikal-T1 CCU IDs list with the new IDs, which will be used to access the corresponding reset controls. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220929225402.9696-7-Sergey.Semin@baikalelectronics.ru Signed-off-by: Stephen Boyd <sboyd@kernel.org> |
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AngeloGioacchino Del Regno
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f098c088f9 |
dt-bindings: reset: Add bindings for MT6795 Helio X10 reset controllers
Add the reset controller bindings for MT6795. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220921091455.41327-4-angelogioacchino.delregno@collabora.com Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> |
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AngeloGioacchino Del Regno
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697b551e29 |
dt-bindings: reset: mt8195: Add resets for USB/PCIe t-phy port 1
Add the reset index for USBSIF P1 (T-PHY port 1), used as either USB or PCI-Express PHY reset. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220720102817.237483-2-angelogioacchino.delregno@collabora.com Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> |
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AngeloGioacchino Del Regno
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7e5073a74f |
dt-bindings: reset: mt8195: Add resets for PCIE controllers
Add the reset index for PCIe P0 and P1 (PCIe0, PCIe1) on MT8195. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220629105205.173471-2-angelogioacchino.delregno@collabora.com Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> |
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Linus Torvalds
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f7cdaeeab8 |
power supply and reset changes for the v6.0 series
power-supply core: - none drivers: - pwr-mlxbf: new reset driver for Mellanox BlueField - at91-reset: SAMA7G5 support - ab8500: continue refurbishing - misc. minor fixes -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEE72YNB0Y/i3JqeVQT2O7X88g7+poFAmL1g+cACgkQ2O7X88g7 +pqlSQ//bHOcpSskI+fVDkPNbInVdOW7eK+cVdkNyeeEgZMz86C7fcQQ3/LwLhpj Jw3PFhIKklNR6dk+hE3Q6Jw0gzMSBIeCILCPuHLOYc4rWgduUzTEO6gCxy+jtDt+ cfUfP9RsfU47RYT6f5XL4K2Qlu0Plhpro+P7nECYubPRwYVnrpiMYDrOWNb68Yyb gcCjJN21nrQ4fJy/Qai1nUjlKAKJOmL6LBO/qe0EjVSllkGGGmAIDfolvXXmS1ku HZ5IEnpFp6usiXa52Q06QyWF6yp2WFsF1gACfWnimpj3lpPKcY4XSGR/rtAtu1ed qgxjmXoKCEy8z5WLjMlgNzOsVTMNSZyU4MWqrb4zQkR2GyaEqH2K1Hbp22Eu8qDC EHWel114aSHAooOhCXbl1mp7t+1aS+72buagmV2KuGMUMBf0jLKcTJahN0Czek3O EwrlN9INIMgcXZ2Ze7dEO6pJcdUov/fiOlB4rXE/cFIlSILT1dTuBPJCKrAqTePV 7QMYMmTvlSEgdTxgc7c4FaP9+ILxkZ1EgKDvxETKLImevXyecngep8S+9uq2cVkA lYdt33MnOHMx0AktFjKS0EEU1zkYN0z+yT3/0uuqzfT5/5xdvIqedXqkncl3Mdqq Ckdnya9n5NGmQXDr+0iuKBe510+nZX3yf1exTBbogOf97uBYiR8= =ulQI -----END PGP SIGNATURE----- Merge tag 'for-v6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-power-supply Pull power supply and reset updates from Sebastian Reichel: "No core patches, only driver updates: - pwr-mlxbf: new reset driver for Mellanox BlueField - at91-reset: SAMA7G5 support - ab8500: continue refurbishing - misc minor fixes" * tag 'for-v6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-power-supply: (29 commits) power: supply: olpc_battery: Hold the reference returned by of_find_compatible_node power: supply: ab8500: add missing destroy_workqueue in ab8500_charger_bind power: supply: ab8500: Remove flush_scheduled_work() call. power: supply: ab8500_fg: drop duplicated 'is' in comment power: supply: ab8500: Drop external charger leftovers power: supply: ab8500: Add MAINTAINERS entry dt-bindings: power: reset: qcom,pshold: convert to dtschema power: supply: Fix typo in power_supply_check_supplies power: reset: pwr-mlxbf: change rst_pwr_hid and low_pwr_hid from global to local variables power: reset: pwr-mlxbf: add missing include power: reset: at91-reset: add support for SAMA7G5 power: reset: at91-reset: add reset_controller_dev support power: reset: at91-reset: add at91_reset_data power: reset: at91-reset: document structures and enums dt-bindings: reset: add sama7g5 definitions dt-bindings: reset: atmel,at91sam9260-reset: add sama7g5 bindings dt-bindings: reset: convert Atmel/Microchip reset controller to YAML power: reset: pwr-mlxbf: add BlueField SoC power control driver power: supply: ab8500: Exit maintenance if too low voltage power: supply: ab8500: Respect charge_restart_voltage_uv ... |
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Linus Torvalds
|
36001a2fa6 |
The clk core gains a new set of APIs that allow drivers to both acquire clks
and prepare and enable them at the same time. This also comes with devm support
so that drivers can make a single call to get and prepare and enable the clk
and have that all undone when their driver is removed. Many folks have
requested this feature over the years, but we've had disagreements about how to
implement it and if it was worthwhile to encourage drivers to use such an API.
Now it's here, so let's see how it goes. I hope that by introducing this API we
can identify drivers that would benefit from further consolidation of clk API
usage, possibly by moving such logic to the bus layer and out of drivers
altogether.
Outside of that major API update, we have the usual collection of driver
updates. A few new SoCs are supported, mostly Qualcomm and Renesas this time
around. Then we have the long tail of non-critical fixes and minor feature
additions to various clk drivers. And finally more clk provider migration to
struct clk_parent_data, reducing boot times in the process.
Core:
- devm helpers for clk_get() + clk_prepare() and clk_enable()
New Drivers:
- Support for the camera clock controller in Qualcomm SM8450 and
the display and gpu clock controllers in Qualcomm SM8350
- Add support for the Renesas RZ/Five SoC
Updates:
- Various fixes, new clocks and USB GDSCs are introduced for Qualcomm IPQ8074
- Fixes to Qualcomm MSM8939 for issues introduced by inheriting the MSM8916
GCC driver
- Support for a new type of voteable GDSCs used by Qualcomm SC8280XP PCIe
GDSCs
- Qualcomm SC8280XP pipe clocks transitioned to the new phy-mux implementation
- Qualcomm MSM8996 GCC, RPM clock driver and some clocks in MSM8994 GCC are
migrated to use clk_parent_data
- Corrected the topology for Titan (camera) GDSCs on Qualcomm SDM845 and
SM8250
- Qualcomm MSM8916 gains more possible frequencies for its GP clocks.
- The GCC and tsens handling on Qualcomm MSM8960 is reworked to mimic the
design in IPQ8074 to allow the GCC driver to probe earlier.
- The regulator based mmcx supply for Qualcomm dispcc and videocc is dropped,
as the only upstream target that adapted this interface was transitioned
several kernel versions ago
- Qualcomm GDSCs found to be enabled at boot will now reflect in the enable
count of the supply, as was done with the regulator supplies previously
- Correct adc1, nic_media and edma1's parents for NXP i.MX93
- rdiv, mfd values, the return rate in recalc_rate and add more frequencies in
the table for fracn-gppll on i.MX
- Remove Allwinner workaround logic/compatible in fixed factor code
- MediaTek clk driver cleanups
- Add reset support to more MediaTek clk drivers
- deduplicate Allwinner ccu_clks arrays
- Allwinner H6 GPU DFS support
- Adjust Allwinner Kconfig to limit choice
- Fix initconst confusion on Renesas R-Car Gen4
- Add GPT/POEG (PWM) clocks and resets on Renesas RZ/G2L
- Add PFC and WDT clocks and resets on Renesas RZ/V2M
- Add thermal, SDHI, Z (CPU core), PCIe, and HSCIF (serial) clocks on
Renesas R-Car S4-8
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"The clk core gains a new set of APIs that allow drivers to both
acquire clks and prepare and enable them at the same time. This also
comes with devm support so that drivers can make a single call to get
and prepare and enable the clk and have that all undone when their
driver is removed.
Many folks have requested this feature over the years, but we've had
disagreements about how to implement it and if it was worthwhile to
encourage drivers to use such an API.
Now it's here, so let's see how it goes.
I hope that by introducing this API we can identify drivers that would
benefit from further consolidation of clk API usage, possibly by
moving such logic to the bus layer and out of drivers altogether.
Outside of that major API update, we have the usual collection of
driver updates. A few new SoCs are supported, mostly Qualcomm and
Renesas this time around. Then we have the long tail of non-critical
fixes and minor feature additions to various clk drivers.
And finally more clk provider migration to struct clk_parent_data,
reducing boot times in the process.
Summary:
Core:
- devm helpers for clk_get() + clk_prepare() and clk_enable()
New Drivers:
- Support for the camera clock controller in Qualcomm SM8450 and the
display and gpu clock controllers in Qualcomm SM8350
- Add support for the Renesas RZ/Five SoC
Updates:
- Various fixes, new clocks and USB GDSCs are introduced for Qualcomm
IPQ8074
- Fixes to Qualcomm MSM8939 for issues introduced by inheriting the
MSM8916 GCC driver
- Support for a new type of voteable GDSCs used by Qualcomm SC8280XP
PCIe GDSCs
- Qualcomm SC8280XP pipe clocks transitioned to the new phy-mux
implementation
- Qualcomm MSM8996 GCC, RPM clock driver and some clocks in MSM8994
GCC are migrated to use clk_parent_data
- Corrected the topology for Titan (camera) GDSCs on Qualcomm SDM845
and SM8250
- Qualcomm MSM8916 gains more possible frequencies for its GP clocks.
- The GCC and tsens handling on Qualcomm MSM8960 is reworked to mimic
the design in IPQ8074 to allow the GCC driver to probe earlier.
- The regulator based mmcx supply for Qualcomm dispcc and videocc is
dropped, as the only upstream target that adapted this interface
was transitioned several kernel versions ago
- Qualcomm GDSCs found to be enabled at boot will now reflect in the
enable count of the supply, as was done with the regulator supplies
previously
- Correct adc1, nic_media and edma1's parents for NXP i.MX93
- rdiv, mfd values, the return rate in recalc_rate and add more
frequencies in the table for fracn-gppll on i.MX
- Remove Allwinner workaround logic/compatible in fixed factor code
- MediaTek clk driver cleanups
- Add reset support to more MediaTek clk drivers
- deduplicate Allwinner ccu_clks arrays
- Allwinner H6 GPU DFS support
- Adjust Allwinner Kconfig to limit choice
- Fix initconst confusion on Renesas R-Car Gen4
- Add GPT/POEG (PWM) clocks and resets on Renesas RZ/G2L
- Add PFC and WDT clocks and resets on Renesas RZ/V2M
- Add thermal, SDHI, Z (CPU core), PCIe, and HSCIF (serial) clocks on
Renesas R-Car S4-8"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (124 commits)
clk: fixed-factor: Introduce *clk_hw_register_fixed_factor_parent_hw()
clk: mux: Introduce devm_clk_hw_register_mux_parent_hws()
clk: divider: Introduce devm_clk_hw_register_divider_parent_hw()
clk: qcom: gcc-msm8994: use parent_hws for gpll0/4
clk: qcom: clk-rpm: convert to parent_data API
dt-bindings: clock: fix wrong clock documentation for qcom,rpmcc
clk: qcom: gcc-msm8939: Add missing USB HS system clock frequencies
clk: qcom: gcc-msm8939: Add missing MDSS MDP clock frequencies
clk: qcom: gcc-msm8939: Add missing CAMSS CPP clock frequencies
clk: qcom: gcc-msm8939: Fix venus0_vcodec0_clk frequency definitions
clk: qcom: gcc-msm8939: Add missing CAMSS CCI bus clock
clk: qcom: gcc-msm8939: Fix weird field spacing in ftbl_gcc_camss_cci_clk
clk: qcom: gdsc: Bump parent usage count when GDSC is found enabled
clk: qcom: Drop mmcx gdsc supply for dispcc and videocc
clk: qcom: fix build error initializer element is not constant
clk: sprd: Add dt-bindings include file for UMS512
dt-bindings: clk: sprd: Add bindings for ums512 clock controller
clk: sunxi-ng: sun50i: h6: Modify GPU clock configuration to support DFS
dt-bindings: clock: qcom,gcc-msm8996: add more GCC clock sources
clk: qcom: add support for SM8350 DISPCC
...
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Linus Torvalds
|
dd65b96492 |
ARM: new SoC support for 6.0
This adds initial support for two SoC families that have been under review for a while. In both cases, the origonal idea was to have a minimally functional version, but we ended up leaving out the clk drivers that are still under review and will be merged through the corresponding subsystem tree. The Nuvoton NPCM8xx is a 64-bit Baseboard Management Controller and based on the 32-bit NPCM7xx family but is now getting added to arch/arm64 as well. Sunplus SP7021, also known as Plus1, is a general-purpose System-in-Package design based on the 32-bit Cortex-A7 SoC on the main chip, plus an I/O chip and memory in the same -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmLo+24ACgkQmmx57+YA GNkPVw//XAC/uK7WR4oz1D1YaPPNhEvFa6hV1gjGB7Iif72SzyDJmC+36MATU/AY neQjCOLJMhxI0hpDGY9nLYe+aP1C6vD32zsjffjt/+s9em+YZZCUkRJuQ5xO3fID Uk8ZAnCIcOqX9sjXr9ChW8irlcWFbKzhgWXnPqwQmycIaE7QVz1wx32dbc64YuAK S+290U8wbj8bukr33TyZPMdYlfqNU3c1W+dCaeVsQlX1juoHEV3stmIjslRefd6X Jre22YJE41VlPufZej76nHXuVnjKf54Oi347TcbPOWNDtEAIESt3mzKy+zICBT2p v01rNBf0SogyOtSbWDPTFCAH9W9hujSOJIUOWpbOLaPdfElXxcoTBwj2e2LMoW0k ke7YR1m6FKDam5GFU9Oe98CWIiVm/GnTA5mnhhETU1QTXQ3KeZ+Z8X779YuSWPv9 kJuOPRSk9NdcfRtxZz1vpCvhv/2hBbeBuz+GZi3bisMWdvVqS3lFqVbr6kziQbJZ kE6KJH48FdL0VLVvuy+aNSF2umLT42b+5+cmQFuP2zePQgo1DEMKEtFXpZjQJbha 3iu3sHnieOFMLcbNzbqSz2im3yYNBjl1M5qoGEXaw3Rkzqiht0kMNvAa4LmAejbh E+5BIczwWNbaUKgToV1ij65O4a78Bw98m2SIS7awEZC5MW/nXYA= =7Id+ -----END PGP SIGNATURE----- Merge tag 'arm-newsoc-6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM new SoC support from Arnd Bergmann: "This adds initial support for two SoC families that have been under review for a while. In both cases, the origonal idea was to have a minimally functional version, but we ended up leaving out the clk drivers that are still under review and will be merged through the corresponding subsystem tree. The Nuvoton NPCM8xx is a 64-bit Baseboard Management Controller and based on the 32-bit NPCM7xx family but is now getting added to arch/arm64 as well. Sunplus SP7021, also known as Plus1, is a general-purpose System-in-Package design based on the 32-bit Cortex-A7 SoC on the main chip, plus an I/O chip and memory in the same" * tag 'arm-newsoc-6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (25 commits) MAINTAINERS: rectify entry for ARM/NUVOTON NPCM ARCHITECTURE arm64: defconfig: Add Nuvoton NPCM family support arm64: dts: nuvoton: Add initial NPCM845 EVB device tree arm64: dts: nuvoton: Add initial NPCM8XX device tree arm64: npcm: Add support for Nuvoton NPCM8XX BMC SoC dt-bindings: arm: npcm: Add nuvoton,npcm845 GCR compatible string dt-bindings: arm: npcm: Add nuvoton,npcm845 compatible string dt-bindings: arm: npcm: Add maintainer reset: npcm: Add NPCM8XX support dt-bindings: reset: npcm: Add support for NPCM8XX reset: npcm: using syscon instead of device data ARM: dts: nuvoton: add reset syscon property dt-bindings: reset: npcm: add GCR syscon property dt-binding: clk: npcm845: Add binding for Nuvoton NPCM8XX Clock dt-bindings: watchdog: npcm: Add npcm845 compatible string dt-bindings: timer: npcm: Add npcm845 compatible string ARM: dts: Add Sunplus SP7021-Demo-V3 board device tree ARM: sp7021_defconfig: Add Sunplus SP7021 defconfig ARM: sunplus: Add initial support for Sunplus SP7021 SoC irqchip: Add Sunplus SP7021 interrupt controller driver ... |
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Mikko Perttunen
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63a6ef2360 |
dt-bindings: Add headers for Host1x and VIC on Tegra234
Add clock, memory controller, powergate and reset dt-binding headers for Host1x and VIC on Tegra234. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com> |
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Qin Jian
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55bfc376b8 |
dt-bindings: reset: Add bindings for SP7021 reset driver
Add documentation to describe Sunplus SP7021 reset driver bindings. Signed-off-by: Qin Jian <qinjian@cqplus1.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Thierry Reding
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b0aedf342b |
dt-bindings: Add Tegra234 MGBE clocks and resets
Add the clocks and resets used by the MGBE Ethernet hardware found on Tegra234 SoCs. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Bhadram Varka <vbhadram@nvidia.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com> |
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Claudiu Beznea
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5994f58977 |
dt-bindings: reset: add sama7g5 definitions
Add reset bindings for SAMA7G5. At the moment only USB PHYs are included. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> |
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Rex-BC Chen
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5ea61b478f |
dt-bindings: reset: mediatek: Add infra_ao reset index for MT8186
To support reset of infra_ao, add the index of infra_ao reset of thermal/svs for MT8186. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220523093346.28493-18-rex-bc.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org> |
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Rex-BC Chen
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fb91526b5f |
dt-bindings: reset: mediatek: Add infra_ao reset index for MT8192/MT8195
To support reset of infra_ao, add the index of infra_ao reset of thermal/svs/pcei for MT8192 and thermal/svs for MT8195. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> [Nícolas: Test for MT8192] Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20220523093346.28493-14-rex-bc.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org> |
||
|
Akhil R
|
3ffb20f5c7 |
dt-bindings: Add headers for Tegra234 GPCDMA
Add reset and IOMMU header for Tegra234 GPCDMA Signed-off-by: Akhil R <akhilrajeev@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com> |
||
|
Linus Torvalds
|
96752be4d7 |
linux-watchdog 5.19-rc1 tag
-----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.14 (GNU/Linux) iEYEABECAAYFAmKXhXYACgkQ+iyteGJfRsoTRQCgre6Jur9IDwegaxnbFpgZTde9 wf4AnAo5l8Vyz7EQLG1YSPjzr5kmK263 =Xdkg -----END PGP SIGNATURE----- Merge tag 'linux-watchdog-5.19-rc1' of git://www.linux-watchdog.org/linux-watchdog Pull watchdog updates from Wim Van Sebroeck: - Add MediaTek MT8186 support - Add Mediatek MT7986 reset-controller support - Add i.MX93 support - Add watchdog driver for Sunplus SP7021 - Add SC8180X and SC8280XP compatibles - Add Renesas RZ/N1 Watchdog driver and support for RZ/N1 - rzg2l_wdt improvements and fixes - Several other improvements and fixes * tag 'linux-watchdog-5.19-rc1' of git://www.linux-watchdog.org/linux-watchdog: (38 commits) watchdog: ts4800_wdt: Fix refcount leak in ts4800_wdt_probe dt-bindings: watchdog: renesas,wdt: R-Car V3U is R-Car Gen4 watchdog: Add Renesas RZ/N1 Watchdog driver dt-bindings: watchdog: renesas,wdt: Add support for RZ/N1 watchdog: wdat_wdt: Stop watchdog when uninstalling module watchdog: wdat_wdt: Stop watchdog when rebooting the system watchdog: wdat_wdt: Using the existing function to check parameter timeout dt-bindings: watchdog: da9062: add watchdog timeout mode dt-bindings: watchdog: renesas,wdt: Document RZ/G2UL SoC watchdog: iTCO_wdt: Using existing macro define covers more scenarios watchdog: rti-wdt: Fix pm_runtime_get_sync() error checking dt-bindings: watchdog: Add SC8180X and SC8280XP compatibles watchdog: rti_wdt: Fix calculation and evaluation of preset heartbeat dt-bindings: watchdog: uniphier: Use unevaluatedProperties watchdog: sp805: disable watchdog on remove watchdog: da9063: optionally disable watchdog during suspend dt-bindings: mfd: da9063: watchdog: add suspend disable option dt-bindings: watchdog: sunxi: clarify clock support dt-bindings: watchdog: sunxi: fix F1C100s compatible watchdog: Add watchdog driver for Sunplus SP7021 ... |
||
|
Linus Torvalds
|
6b0e34a030 |
Mainly driver updates this time around. There's a single patch to the core clk
framework that simplifies a runtime PM call. Otherwise the majority of the diff
falls to a few SoC drivers: Qualcomm, STM32 and MediaTek. Those SoCs gain some
new hardware support and what comes along with that is quite a few lines of
data and some clk_ops code. Beyond the new hardware support we have the usual
pile of driver updates that add missing clks on already supported SoCs or fix
up problems like bad clk tree descriptions. It's nice to see that more drivers
are moving to clk_hw based APIs too.
New Drivers:
- Add STM32MP13 RCC driver (Reset Clock Controller)
- MediaTek MT8186 SoC clk support
- Airoha EN7523 SoC system clocks
- Clock driver for exynosautov9 SoC
- Renesas R-Car V4H and RZ/V2M SoCs
- Renesas RZ/G2UL SoC
- LPASS clk driver for Qualcomm sc7280 SoC
- GCC clk driver for Qualcomm SC8280XP SoC
Updates:
- SDCC uses floor clk ops on Qualcomm MSM8976
- Add modem reset and fix RPM clks on Qualcomm MSM8976
- Add the two missing CLKOUT clocks for U8500/DB8500 SoC
- Mark some clks critical on Ingenic X1000
- Convert ux500 to clk_hw
- Move MediaTek driver to clk_hw provider APIs
- Use i2c driver probe_new to avoid id scans
- Convert a number of Rockchip dt bindings to YAML
- Mark hclk_vo critical on Rockchip rk3568
- Use pm_runtime_resume_and_get to fix pm_runtime_get_sync() usage
- Various cleanups like memory allocation error checks and plugged leaks
- Allwinner H6 RTC clock support
- Allwinner H616 32 kHz clock support
- Add the Universal Flash Storage clock on Renesas R-Car S4-8
- Add I2C, SSIF-2 (sound), USB, CANFD, OSTM (timer), WDT, SPI Multi
I/O Bus, RSPI, TSU (thermal), and ADC clocks and resets on Renesas RZ/G2UL
- Add display clock support on Renesas RZ/G2L
- Add RPC (QSPI/HyperFlash) clocks on Renesas R-Car E3 and D3
- Add 27 MHz phy PLL ref clock on i.MX
- Add mcore_booted module parameter to tell kernel M core has already booted
for i.MX
- Remove snvs clock on i.MX because it was for secure world only
- Add dt bindings for i.MX8MN GPT
- Add DISP2 pixel clock for i.MX8MP
- Add clkout1/2 for i.MX8MP
- Fix parent clock of ubs_root_clk for i.MX8MP
- Implement better RCG parking on Qualcomm SoCs using the shared RCG clk ops
- Kerneldoc fixes
- Switch Tegra BPMP to determine_rate clk op
- Add a pointer to dt schema for generic clock bindings
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"Mainly driver updates this time around.
There's a single patch to the core clk framework that simplifies a
runtime PM call. Otherwise the majority of the diff falls to a few SoC
drivers: Qualcomm, STM32 and MediaTek. Those SoCs gain some new
hardware support and what comes along with that is quite a few lines
of data and some clk_ops code.
Beyond the new hardware support we have the usual pile of driver
updates that add missing clks on already supported SoCs or fix up
problems like bad clk tree descriptions. It's nice to see that more
drivers are moving to clk_hw based APIs too.
New Drivers:
- Add STM32MP13 RCC driver (Reset Clock Controller)
- MediaTek MT8186 SoC clk support
- Airoha EN7523 SoC system clocks
- Clock driver for exynosautov9 SoC
- Renesas R-Car V4H and RZ/V2M SoCs
- Renesas RZ/G2UL SoC
- LPASS clk driver for Qualcomm sc7280 SoC
- GCC clk driver for Qualcomm SC8280XP SoC
Updates:
- SDCC uses floor clk ops on Qualcomm MSM8976
- Add modem reset and fix RPM clks on Qualcomm MSM8976
- Add the two missing CLKOUT clocks for U8500/DB8500 SoC
- Mark some clks critical on Ingenic X1000
- Convert ux500 to clk_hw
- Move MediaTek driver to clk_hw provider APIs
- Use i2c driver probe_new to avoid id scans
- Convert a number of Rockchip dt bindings to YAML
- Mark hclk_vo critical on Rockchip rk3568
- Use pm_runtime_resume_and_get to fix pm_runtime_get_sync() usage
- Various cleanups like memory allocation error checks and plugged
leaks
- Allwinner H6 RTC clock support
- Allwinner H616 32 kHz clock support
- Add the Universal Flash Storage clock on Renesas R-Car S4-8
- Add I2C, SSIF-2 (sound), USB, CANFD, OSTM (timer), WDT, SPI Multi
I/O Bus, RSPI, TSU (thermal), and ADC clocks and resets on Renesas
RZ/G2UL
- Add display clock support on Renesas RZ/G2L
- Add RPC (QSPI/HyperFlash) clocks on Renesas R-Car E3 and D3
- Add 27 MHz phy PLL ref clock on i.MX
- Add mcore_booted module parameter to tell kernel M core has already
booted for i.MX
- Remove snvs clock on i.MX because it was for secure world only
- Add dt bindings for i.MX8MN GPT
- Add DISP2 pixel clock for i.MX8MP
- Add clkout1/2 for i.MX8MP
- Fix parent clock of ubs_root_clk for i.MX8MP
- Implement better RCG parking on Qualcomm SoCs using the shared RCG
clk ops
- Kerneldoc fixes
- Switch Tegra BPMP to determine_rate clk op
- Add a pointer to dt schema for generic clock bindings"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (168 commits)
Revert "clk: qcom: regmap-mux: add pipe clk implementation"
Revert "clk: qcom: gcc-sc7280: use new clk_regmap_mux_safe_ops for PCIe pipe clocks"
Revert "clk: qcom: gcc-sm8450: use new clk_regmap_mux_safe_ops for PCIe pipe clocks"
clk: bcm: rpi: Use correct order for the parameters of devm_kcalloc()
clk: stm32mp13: add safe mux management
clk: stm32mp13: add multi mux function
clk: stm32mp13: add all STM32MP13 kernel clocks
clk: stm32mp13: add all STM32MP13 peripheral clocks
clk: stm32mp13: manage secured clocks
clk: stm32mp13: add composite clock
clk: stm32mp13: add stm32 divider clock
clk: stm32mp13: add stm32_gate management
clk: stm32mp13: add stm32_mux clock management
clk: stm32: Introduce STM32MP13 RCC drivers (Reset Clock Controller)
dt-bindings: rcc: stm32: add new compatible for STM32MP13 SoC
clk: ti: clkctrl: replace usage of found with dedicated list iterator variable
clk: ti: composite: Prefer kcalloc over open coded arithmetic
dt-bindings: clock: exynosautov9: correct count of NR_CLK
clk: mediatek: mt8173: Switch to clk_hw provider APIs
clk: mediatek: Switch to clk_hw provider APIs
...
|
||
|
Linus Torvalds
|
cc3c470ae4 |
ARM: driver changes for 5.19
There are minor updates to SoC specific drivers for chips by Rockchip,
Samsung, NVIDIA, TI, NXP, i.MX, Qualcomm, and Broadcom. Noteworthy
driver changes include:
- Several conversions of DT bindings to yaml format.
- Renesas adds driver support for R-Car V4H, RZ/V2M and RZ/G2UL SoCs.
- Qualcomm adds a bus driver for the SSC (Snapdragon Sensor Core),
and support for more chips in the RPMh power domains and the soc-id.
- NXP has a new driver for the HDMI blk-ctrl on i.MX8MP.
- Apple M1 gains support for the on-chip NVMe controller, making it
possible to finally use the internal disks. This also includes SoC
drivers for their RTKit IPC and for the SART DMA address filter.
For other subsystems that merge their drivers through the SoC tree,
we have
- Firmware drivers for the ARM firmware stack including TEE, OP-TEE,
SCMI and FF-A get a number of smaller updates and cleanups. OP-TEE
now has a cache for firmware argument structures as an optimization,
and SCMI now supports the 3.1 version of the specification.
- Reset controller updates to Amlogic, ASpeed, Renesas and ACPI drivers
- Memory controller updates for Tegra, and a few updates for other
platforms.
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Merge tag 'arm-drivers-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM driver updates from Arnd Bergmann:
"There are minor updates to SoC specific drivers for chips by Rockchip,
Samsung, NVIDIA, TI, NXP, i.MX, Qualcomm, and Broadcom.
Noteworthy driver changes include:
- Several conversions of DT bindings to yaml format.
- Renesas adds driver support for R-Car V4H, RZ/V2M and RZ/G2UL SoCs.
- Qualcomm adds a bus driver for the SSC (Snapdragon Sensor Core),
and support for more chips in the RPMh power domains and the
soc-id.
- NXP has a new driver for the HDMI blk-ctrl on i.MX8MP.
- Apple M1 gains support for the on-chip NVMe controller, making it
possible to finally use the internal disks. This also includes SoC
drivers for their RTKit IPC and for the SART DMA address filter.
For other subsystems that merge their drivers through the SoC tree, we
have
- Firmware drivers for the ARM firmware stack including TEE, OP-TEE,
SCMI and FF-A get a number of smaller updates and cleanups. OP-TEE
now has a cache for firmware argument structures as an
optimization, and SCMI now supports the 3.1 version of the
specification.
- Reset controller updates to Amlogic, ASpeed, Renesas and ACPI
drivers
- Memory controller updates for Tegra, and a few updates for other
platforms"
* tag 'arm-drivers-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (159 commits)
memory: tegra: Add MC error logging on Tegra186 onward
memory: tegra: Add memory controller channels support
memory: tegra: Add APE memory clients for Tegra234
memory: tegra: Add Tegra234 support
nvme-apple: fix sparse endianess warnings
soc/tegra: pmc: Document core domain fields
soc: qcom: pdr: use static for servreg_* variables
soc: imx: fix semicolon.cocci warnings
soc: renesas: R-Car V3U is R-Car Gen4
soc: imx: add i.MX8MP HDMI blk-ctrl
soc: imx: imx8m-blk-ctrl: Add i.MX8MP media blk-ctrl
soc: imx: add i.MX8MP HSIO blk-ctrl
soc: imx: imx8m-blk-ctrl: set power device name
soc: qcom: llcc: Add sc8180x and sc8280xp configurations
dt-bindings: arm: msm: Add sc8180x and sc8280xp LLCC compatibles
soc/tegra: pmc: Select REGMAP
dt-bindings: reset: st,sti-powerdown: Convert to yaml
dt-bindings: reset: st,sti-picophyreset: Convert to yaml
dt-bindings: reset: socfpga: Convert to yaml
dt-bindings: reset: snps,axs10x-reset: Convert to yaml
...
|
||
|
Gabriel Fernandez
|
722dc8a1d5 |
dt-bindings: rcc: stm32: add new compatible for STM32MP13 SoC
New compatible to manage clock and reset of STM32MP13 SoC. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Link: https://lore.kernel.org/r/20220516070600.7692-2-gabriel.fernandez@foss.st.com Signed-off-by: Stephen Boyd <sboyd@kernel.org> |
||
|
Arnd Bergmann
|
82706d6fb1 |
MT8195:
- add evaluation and demo board MT8192: - add new nodes: pwrap, PMIC, scp, USB, efuse, IOMMU, smi, DPI, PCIe, SPMI, audio system, MMC and video enconder - add evaluation board MT8183: - fix dtschema issues - update compatible for the display ambient light processor (disp-aal) - fix dtschema warning for the pumpki board MT8173: - add power domains to the video enconder nodes - add GCE support to the display mutex node MT7622: - specify number of DMA requests explicitely - specify level 2 cache topology - add SPI-NAND flash device - fix dtschema warnings for the System Companion Processor (SCP) -----BEGIN PGP SIGNATURE----- iQJLBAABCAA1FiEEUdvKHhzqrUYPB/u8L21+TfbCqH4FAmJ+QQQXHG1hdHRoaWFz LmJnZ0BnbWFpbC5jb20ACgkQL21+TfbCqH6MUw//d15n/edr21mmD/km512t/JJ+ u8ke9XGDnULk/bG2bFW+F+9wxsgR3Y6ULcoXIjYyRjOfrysBssFRPnz4hU1pIDEX YFQFhoTlV86DFJUw517bwuN59/V8UQB3kIv6FgxoYumec1QJ74x1kAdLYBi1MGGW Yi9DFSBMxbK6tFMAYRLut2r62NK25SqH55oPfJnzVcL7dUGN/nL3VW+3vUxrRdul SNbQAzIlHMj47IApdnWsllYL+SmYX7O71rrXYnLSGTyKU53iu9jEo6QNy+iytHLY qW32Y2bu0rA9pw5MtJjYOTFjLdlXe33h6xuS/3f3EvlKyS6L3MA3iUMBnGiORsKz USNdZN4Z1qtNVd7775NKQOpx6m2RAHaQUeXwwOvvf9wU9jgf5YI3cLDoG/0osVQb s/LCZDZD3/h36Exy1PTlFaHlqRR4iaIHD1UzTxS1ST2+OosokT3vIanfTA3G4QjN /gs0AMD9IrMDZtu79rUmDE26rHF+wmy2QsRDo1VxB0QWGQjFhCn0VsV2K+uFyG9j VKgK/n7ouwSN2+LjyLFJV2C55zRy/NQ6kIxvIohuLxWncIuqKEkvU22iLlNECsI3 VT4xQV8AWLp38pXNSD29oj/FyojjJOJgFgSHDst5tPfaswdckMvodWUVIS8tgiAY THdQekFc5B+HwmTSjZE= =Ewdg -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmJ+zQAACgkQmmx57+YA GNlrAw/9G/X8jojghV0Uq1NOm+QtmPQ9pusNttjeviImZd2RAf4rqJnCHEwcWAsf tXiu2+YVTgUZdwJO73nvswfbQ3sLBGSkw0N+nDNMfqqSNytQSTSokDp8NNr9pi4t 914shAoz0mMk6I932attImfaWOoWUR9zOGhGJi9M/NnOkBsHHhANr4vldEscxkuc ecOFknHp8ZfVuRfDJcR4opbVUvCmeRbnrQWgG2ud9YPsGB4MsRBvnzZDdyFVFz/q HlobUjpeW1+uH87lpxyz+NSex3V39falXjSDL51rIG2p7lCVb1wbi+lEDnc8uy28 DuLN1N+LdMBOyoMb077TCtquWRKEbFOmJ/8SzD78a5BoyV0Hxhp3EGteAuZ2rx/E rPAyy+dNAVmwMaIiSYeb/Y5DuE9kjuxb5NpNvIaZEDdkPZfIZiMfKnOziGHQncPp p+JbuDW6z+XMcDa7S4vlCmGRF5xqHknSFs9Ivnm/p64Cd5fK/enzc5On/gsB/fKP mXVbESme88tev22JG0rHgFVKZB29wOJLv9mMJzpJQGkmqVy32nO7unUc6tq7G6A5 idP76etCgx3FCttCuq2s6CZCwcVYlHee17JnIMl9Y3gZccAsT3rMtt0TK4R6OuFN oP3+8286Kc3TW0/V3zvowzT+h7sqxMFJyXWKyrcRvA2ConoO0y8= =kcWT -----END PGP SIGNATURE----- Merge tag 'v5.18-next-dts64' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/dt MT8195: - add evaluation and demo board MT8192: - add new nodes: pwrap, PMIC, scp, USB, efuse, IOMMU, smi, DPI, PCIe, SPMI, audio system, MMC and video enconder - add evaluation board MT8183: - fix dtschema issues - update compatible for the display ambient light processor (disp-aal) - fix dtschema warning for the pumpki board MT8173: - add power domains to the video enconder nodes - add GCE support to the display mutex node MT7622: - specify number of DMA requests explicitely - specify level 2 cache topology - add SPI-NAND flash device - fix dtschema warnings for the System Companion Processor (SCP) * tag 'v5.18-next-dts64' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux: (37 commits) arm64: dts: mt8192: Follow binding order for SCP registers arm64: dts: mediatek: add mtk-snfi for mt7622 arm64: dts: mediatek: mt8195-demo: enable uart1 arm64: dts: mediatek: mt8195-demo: Remove input-name property arm64: dts: mediatek: mt8183-pumpkin: fix bad thermistor node name arm64: dts: mt7622: specify the L2 cache topology arm64: dts: mt7622: specify the number of DMA requests arm64: dts: mediatek: pumpkin: Remove input-name property arm64: dts: mediatek: mt8173: Add gce-client-reg handle to disp-mutex arm64: dts: mediatek: Add device-tree for MT8195 Demo board dt-bindings: arm64: dts: mediatek: Add mt8195-demo board arm64: dts: Add mediatek SoC mt8195 and evaluation board arm64: dts: mt8192: Add mmc device nodes arm64: dts: mt8183: Update disp_aal node compatible arm64: dts: mt8192: Add audio-related nodes arm64: dts: mt8192: Add spmi node dt-bindings: arm: Add compatible for Mediatek MT8192 arm64: dts: mt6359: add PMIC MT6359 related nodes arm64: dts: mediatek: mt8173: Add power domain to encoder nodes arm64: dts: mediatek: Get rid of mediatek, larb for MM nodes ... Link: https://lore.kernel.org/r/2cd90ca7-7541-d47a-fec6-b0c64cf74fa3@gmail.com Like the 32-bit branch, this contains an incompatible binding change by removing the mediatek,larb properties from the dts files, so these no longer work with kernels prior to 5.18. Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
||
|
Sam Shih
|
5794dda109 |
dt-bindings: reset: mt7986: Add reset-controller header file
Add infracfg, toprgu, and ethsys reset-controller header file for MT7986 platform. Signed-off-by: Sam Shih <sam.shih@mediatek.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Guenter Roeck <linux@roeck-us.net> Link: https://lore.kernel.org/r/20220105100456.7126-2-sam.shih@mediatek.com Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org> |
||
|
Runyang Chen
|
1d6866e8f1 |
dt-bindings: reset: mt8186: add reset-controller header file
1. Add toprgu reset-controller header file for MT8186. 2. Add DSI software reset bit which is controlled in MMSYS for MT8186. Signed-off-by: Runyang Chen <runyang.chen@mediatek.com> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Link: https://lore.kernel.org/r/20220301054405.25021-3-rex-bc.chen@mediatek.com Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org> |
||
|
Arnd Bergmann
|
1bc44c1e79 |
arm64: tegra: Device tree changes for v5.19-rc1
This adds some improvements on Tegra234 (QSPI, CCPLEX), improves the SDMMC clock speed on Tegra194 and adds the ASRC audio block on various chip generations. Memory controller channels are also added on Tegra186 and later and the missing DFLL reset is added for Tegra210. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAmJ1LsgTHHRyZWRpbmdA bnZpZGlhLmNvbQAKCRDdI6zXfz6zoZKcD/4rxLjWUWGLqTxg1ZtMpWgWpqQAOgn1 lCQCcK75WFOSXWhzFVlvxvDff5RS80vDXHNS9mPT5S9uI2PiqiHKY6v/fOQkddI4 Gk78BGbAtSzCUCoTKYf/iWdiNYhYU7SfgxdZplb8JLAsRCbgxirbnBD+QkMvD4T3 ksTAgUUDespZzJ4NksNWMCWC2iehQu594sXWbMzMTxojC5i1QlanEfX8yg3C5O8C c+NpA9q/JHYg1MiSoDP7Co4Kgj8Bfu0Fxm8DGsaNKSMVh6Ai45TC/5ED7gCBkgLA ObaMQcb6gOnco5LdCAipDMyKml1qiK3YiOa+92CnWocMMWMbg1dlQ8IBoacycOgj hV6/egdcMtmzIK9rj4fGVFH3zbkqw2JeY0IWtZH+5zgJZjsCofIK0PsmgPIewEnj iglEuAWmV4qev/8KB2cbcpRiggLKBZ1o3lpOatKNugNy/T4Aie1C/2tfUEV0Ie07 n/9EkgHHlSXZGwI7zvFwTeiI/IOIySg2BVZsQi//0QVRsj7w9cKv+mHoQ/bZZQFc nXhiMEHhKuWDhbRrlpshI1XUJ5knGz9lCJPrcRV8/9rL0A4zDH+IfH966Jpdepo5 Qh8MdncxOlrflZTOLhbOjemyCU8ieahu8yTcpziyUHqKcxKXDnjJXC6Cg0TpeuX3 QDuWvinVDDHoLw== =KBZh -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmJ1h4sACgkQmmx57+YA GNmbcBAAj+oXraktDfkgmiEg2vcBS92H/ik/09RdifgTomjEQMHNpB+Kp+c6xXuh rHZU/HMqNuuVImmZImTDGqYKXzJMsEckIzBWiXsIP3vNNooJbWyDC5YxPftZqCED tfXfra0U6hCumX03o9l6Tywf2pfawxsO28QFE+xGffKHa53GruIYkj62prXCJWqD GOcCoBkqulNPVoIsQAtCp3JNxnvR3JmYxNlCdbIrTp6zGnhYsMyLFeEdcamS1rCO ZyQ//byFjhTGWr5e3w3LD4ZPekAFN0elWXGLjyz+oitxIAm/jL/4JpZwkbL+qS35 MDO57gQB/nc5wfM2Ojm3rIk2Vs0DeX3V92TcSKPVTqHPqciySb1ftDa5CLzRPyCQ fcLxZHWP1YTHvfcSG0MQLhixp3GW8OhJiSQElqjhWE4LpNmWreElnFAxZ9oiiDTb 58xnU4vaYb7RzqZVmyXuBWaxXH5NQKjri+OFGjbqvH9CI+KVQeH2829otEhbHTad nfBeoZqp9CjzY9ejBWFduCeXLEDO52HGa33BDkJPeO/PENmgmDBZMxo+hJOL2ZZx htpHFlllj0eC/QomGp9zJfadZbslRGigWr9X868whDROhBlL/onFh6iEqPmREhTv M4waPbQynA9928AfYFSxXJmUdvbusxvppU1e4eISWWzC3DyHlHE= =wsbV -----END PGP SIGNATURE----- Merge tag 'tegra-for-5.19-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt arm64: tegra: Device tree changes for v5.19-rc1 This adds some improvements on Tegra234 (QSPI, CCPLEX), improves the SDMMC clock speed on Tegra194 and adds the ASRC audio block on various chip generations. Memory controller channels are also added on Tegra186 and later and the missing DFLL reset is added for Tegra210. * tag 'tegra-for-5.19-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: arm64: tegra: Add missing DFLL reset on Tegra210 arm64: tegra: Add memory controller channels arm64: tegra: Enable ASRC on various platforms arm64: tegra: Add ASRC device on Tegra186 and later arm64: tegra: Update PWM fan node name arm64: tegra: Add node for Tegra234 CCPLEX cluster arm64: tegra: Add QSPI controllers on Tegra234 arm64: tegra: Update SDMMC1/3 clock source for Tegra194 Link: https://lore.kernel.org/r/20220506143005.3916655-5-thierry.reding@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
||
|
Alexandre Torgue
|
5f5d7decf0 |
dt-bindings: reset: stm32mp15: rename RST_SCMI define
As we only have one SCMI instance, it's not necessary to add an index to the name. Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> Acked-by: Rob Herring <robh@kernel.org> |
||
|
Zelong Dong
|
52f988d757 |
dt-bindings: reset: add bindings for the Meson-S4 SoC Reset Controller
Add DT bindings for the Meson-S4 SoC Reset Controller include file. Signed-off-by: Zelong Dong <zelong.dong@amlogic.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20220107023931.13251-3-zelong.dong@amlogic.com |
||
|
Ashish Singhal
|
71f69ffa01 |
arm64: tegra: Add QSPI controllers on Tegra234
This adds the QSPI controllers on the Tegra234 SoC and populates the SPI NOR flash device for the Jetson AGX Orin platform. Signed-off-by: Ashish Singhal <ashishsingha@nvidia.com> Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com> |
||
|
Allen-KH Cheng
|
19c66219e4 |
arm64: dts: mt8192: Add the mmsys reset bit to reset the dsi0
Reset the DSI hardware is needed to prevent different settings between the bootloader and the kernel. Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220318144534.17996-20-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> |
||
|
Linus Torvalds
|
9512433987 |
There's one large change in the core clk framework here. We change how
clk_set_rate_range() works so that the frequency is re-evaulated each time the
rate is changed. Previously we wouldn't let clk providers see a rate that was
different if it was still within the range, which could be bad for power if the
clk could run slower when a range expands. Now the clk provider can decide to
do something differently when the constraints change. This broke Nvidia's clk
driver so we had to wait for the fix for that to bake a little more in -next.
The rate range patch series also introduced a kunit suite for the clk framework
that we're going to extend in the next release. It already made it easy to find
corner cases in the rate range patches so I'm excited to see it cover more clk
code and increase our confidence in core framework patches in the future. I
also added a kunit test for the basic clk gate code and that work will continue
to cover more basic clk types: muxes, dividers, etc.
Beyond the core code we have the usual set of clk driver updates and additions.
Qualcomm again dominates the diffstat here with lots more SoCs being supported
and i.MX follows afer that with a similar number of SoCs gaining clk drivers.
Beyond those large additions there's drivers being modernized to use
clk_parent_data so we can move away from global string names for all the clks
in an SoC. Finally there's lots of little fixes all over the clk drivers for
typos, warnings, and missing clks that aren't critical and get batched up
waiting for the next merge window to open. Nothing super big stands out in the
driver pile. Full details are below.
Core:
- Make clk_set_rate_range() re-evaluate the limits each time
- Introduce various clk_set_rate_range() tests
- Add clk_drop_range() to drop a previously set range
New Drivers:
- i.MXRT1050 clock driver and bindings
- i.MX8DXL clock driver and bindings
- i.MX93 clock driver and bindings
- NCO blocks on Apple SoCs
- Audio clks on StarFive JH7100 RISC-V SoC
- Add support for the new Renesas RZ/V2L SoC
- Qualcomm SDX65 A7 PLL
- Qualcomm SM6350 GPU clks
- Qualcomm SM6125, SM6350, QCS2290 display clks
- Qualcomm MSM8226 multimedia clks
Updates:
- Kunit tests for clk-gate implementation
- Terminate arrays with sentinels and make that clearer
- Cleanup SPDX tags
- Fix typos in comments
- Mark mux table as const in clk-mux
- Make the all_lists array const
- Convert Cirrus Logic CS2000P driver to regmap, yamlify DT binding and add
support for dynamic mode
- Clock configuration on Microchip PolarFire SoCs
- Free allocations on probe error in Mediatek clk driver
- Modernize Mediatek clk driver by consolidating code
- Add watchdog (WDT), I2C, and pin function controller (PFC) clocks on
Renesas R-Car S4-8
- Improve the clocks for the Rockchip rk3568 display outputs (parenting, pll-rates)
- Use of_device_get_match_data() instead of open-coding on Rockchip rk3568
- Reintroduce the expected fractional-divider behaviour that disappeared
with the addition of CLK_FRAC_DIVIDER_POWER_OF_TWO_PS
- Remove SYS PLL 1/2 clock gates for i.MX8M*
- Remove AUDIO MCLK ROOT from i.MX7D
- Add fracn gppll clock type used by i.MX93
- Add new composite clock for i.MX93
- Add missing media mipi phy ref clock for i.MX8MP
- Fix off by one in imx_lpcg_parse_clks_from_dt()
- Rework for the imx pll14xx
- sama7g5: One low priority fix for GCLK of PDMC
- Add DMA engine (SYS-DMAC) clocks on Renesas R-Car S4-8
- Add MOST (MediaLB I/F) clocks on Renesas R-Car E3 and D3
- Add CAN-FD clocks on Renesas R-Car V3U
- Qualcomm SC8280XP RPMCC
- Add some missing clks on Qualcomm MSM8992/MSM8994/MSM8998 SoCs
- Rework Qualcomm GCC bindings and convert SDM845 camera bindig to YAML
- Convert various Qualcomm drivers to use clk_parent_data
- Remove test clocks from various Qualcomm drivers
- Crypto engine clks on Qualcomm IPQ806x + more freqs for SDCC/NSS
- Qualcomm SM8150 EMAC, PCIe, UFS GDSCs
- Better pixel clk frequency support on Qualcomm RCG2 clks
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"There's one large change in the core clk framework here. We change how
clk_set_rate_range() works so that the frequency is re-evaulated each
time the rate is changed. Previously we wouldn't let clk providers see
a rate that was different if it was still within the range, which
could be bad for power if the clk could run slower when a range
expands. Now the clk provider can decide to do something differently
when the constraints change. This broke Nvidia's clk driver so we had
to wait for the fix for that to bake a little more in -next.
The rate range patch series also introduced a kunit suite for the clk
framework that we're going to extend in the next release. It already
made it easy to find corner cases in the rate range patches so I'm
excited to see it cover more clk code and increase our confidence in
core framework patches in the future. I also added a kunit test for
the basic clk gate code and that work will continue to cover more
basic clk types: muxes, dividers, etc.
Beyond the core code we have the usual set of clk driver updates and
additions. Qualcomm again dominates the diffstat here with lots more
SoCs being supported and i.MX follows afer that with a similar number
of SoCs gaining clk drivers. Beyond those large additions there's
drivers being modernized to use clk_parent_data so we can move away
from global string names for all the clks in an SoC. Finally there's
lots of little fixes all over the clk drivers for typos, warnings, and
missing clks that aren't critical and get batched up waiting for the
next merge window to open. Nothing super big stands out in the driver
pile. Full details are below.
Core:
- Make clk_set_rate_range() re-evaluate the limits each time
- Introduce various clk_set_rate_range() tests
- Add clk_drop_range() to drop a previously set range
New Drivers:
- i.MXRT1050 clock driver and bindings
- i.MX8DXL clock driver and bindings
- i.MX93 clock driver and bindings
- NCO blocks on Apple SoCs
- Audio clks on StarFive JH7100 RISC-V SoC
- Add support for the new Renesas RZ/V2L SoC
- Qualcomm SDX65 A7 PLL
- Qualcomm SM6350 GPU clks
- Qualcomm SM6125, SM6350, QCS2290 display clks
- Qualcomm MSM8226 multimedia clks
Updates:
- Kunit tests for clk-gate implementation
- Terminate arrays with sentinels and make that clearer
- Cleanup SPDX tags
- Fix typos in comments
- Mark mux table as const in clk-mux
- Make the all_lists array const
- Convert Cirrus Logic CS2000P driver to regmap, yamlify DT binding
and add support for dynamic mode
- Clock configuration on Microchip PolarFire SoCs
- Free allocations on probe error in Mediatek clk driver
- Modernize Mediatek clk driver by consolidating code
- Add watchdog (WDT), I2C, and pin function controller (PFC) clocks
on Renesas R-Car S4-8
- Improve the clocks for the Rockchip rk3568 display outputs
(parenting, pll-rates)
- Use of_device_get_match_data() instead of open-coding on Rockchip
rk3568
- Reintroduce the expected fractional-divider behaviour that
disappeared with the addition of CLK_FRAC_DIVIDER_POWER_OF_TWO_PS
- Remove SYS PLL 1/2 clock gates for i.MX8M*
- Remove AUDIO MCLK ROOT from i.MX7D
- Add fracn gppll clock type used by i.MX93
- Add new composite clock for i.MX93
- Add missing media mipi phy ref clock for i.MX8MP
- Fix off by one in imx_lpcg_parse_clks_from_dt()
- Rework for the imx pll14xx
- sama7g5: One low priority fix for GCLK of PDMC
- Add DMA engine (SYS-DMAC) clocks on Renesas R-Car S4-8
- Add MOST (MediaLB I/F) clocks on Renesas R-Car E3 and D3
- Add CAN-FD clocks on Renesas R-Car V3U
- Qualcomm SC8280XP RPMCC
- Add some missing clks on Qualcomm MSM8992/MSM8994/MSM8998 SoCs
- Rework Qualcomm GCC bindings and convert SDM845 camera bindig to
YAML
- Convert various Qualcomm drivers to use clk_parent_data
- Remove test clocks from various Qualcomm drivers
- Crypto engine clks on Qualcomm IPQ806x + more freqs for SDCC/NSS
- Qualcomm SM8150 EMAC, PCIe, UFS GDSCs
- Better pixel clk frequency support on Qualcomm RCG2 clks"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (227 commits)
clk: zynq: Update the parameters to zynq_clk_register_periph_clk
clk: zynq: trivial warning fix
clk: Drop the rate range on clk_put()
clk: test: Test clk_set_rate_range on orphan mux
clk: Initialize orphan req_rate
dt-bindings: clock: drop useless consumer example
dt-bindings: clock: renesas: Make example 'clocks' parsable
clk: qcom: gcc-msm8994: Fix gpll4 width
dt-bindings: clock: fix dt_binding_check error for qcom,gcc-other.yaml
clk: rs9: Add Renesas 9-series PCIe clock generator driver
clk: fixed-factor: Introduce devm_clk_hw_register_fixed_factor_index()
clk: visconti: prevent array overflow in visconti_clk_register_gates()
dt-bindings: clk: rs9: Add Renesas 9-series I2C PCIe clock generator
clk: sifive: Move all stuff into SoCs header files from C files
clk: sifive: Add SoCs prefix in each SoCs-dependent data
riscv: dts: Change the macro name of prci in each device node
dt-bindings: change the macro name of prci in header files and example
clk: sifive: duplicate the macro definitions for the time being
clk: qcom: sm6125-gcc: fix typos in comments
clk: ti: clkctrl: fix typos in comments
...
|
||
|
Linus Torvalds
|
dfdc1de642 |
Staging driver update for 5.18-rc1
Here is the big set of staging driver updates for 5.18-rc1.
Loads of tiny cleanups for almost all staging drivers in here, nothing
major at all. Highlights include:
- remove the ashmem Android driver. It is long-dead and if
there are any legacy userspace applications still using it,
the Android kernel images will maintain it, the community
shouldn't care about it anymore
- wfx wifi driver major cleanups. Should be ready to merge out
of staging soon, and will coordinate with the wifi maintainers
after -rc1 is out
- major cleanups and unwinding of the layers of the r8188eu
driver. It's amazing just how many unneeded layers of
abstraction is in there, just when we think it's done, another
is found...
- lots of tiny coding style cleanups in many other staging
drivers.
There will be merge conflict with a fbtft change and the spi driver
changes in your tree, but it's pretty obvious what to do (the function
shouldn't return anything.)
All have been in linux-next for a while with no reported problems.
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Merge tag 'staging-5.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging
Pull staging driver updates from Greg KH:
"Here is the big set of staging driver updates for 5.18-rc1.
Loads of tiny cleanups for almost all staging drivers in here, nothing
major at all. Highlights include:
- remove the ashmem Android driver. It is long-dead and if there are
any legacy userspace applications still using it, the Android
kernel images will maintain it, the community shouldn't care about
it anymore
- wfx wifi driver major cleanups. Should be ready to merge out of
staging soon, and will coordinate with the wifi maintainers after
-rc1 is out
- major cleanups and unwinding of the layers of the r8188eu driver.
It's amazing just how many unneeded layers of abstraction is in
there, just when we think it's done, another is found...
- lots of tiny coding style cleanups in many other staging drivers.
All have been in linux-next for a while with no reported problems"
* tag 'staging-5.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging: (455 commits)
staging: r8188eu: remove unnecessary memset in r8188eu
staging: greybus: introduce pwm_ops::apply
staging: rts5208: Resolve checkpatch.pl issues.
staging: sm750fb: fix naming style
staging: fbtft: Consider type of init sequence values in fbtft_init_display()
staging: fbtft: Constify buf parameter in fbtft_dbg_hex()
staging: mmal-vchiq: clear redundant item named bulk_scratch
mips: dts: ralink: add MT7621 SoC
staging: r8188eu: remove some unused local ieee80211 macros
staging: r8188eu: make rtl8188e_process_phy_info static
staging: r8188eu: remove unused function prototype
staging: r8188eu: remove three unused receive defines
staging: r8188eu: remove unnecessary initializations
staging: rtl8192e: Fix spelling mistake "RESQUEST" -> "REQUEST"
MAINTAINERS: remove the obsolete file entry for staging in ANDROID DRIVERS
staging: r8188eu: proper error handling in rtw_init_drv_sw
staging: r8188eu: call _cancel_timer_ex from _rtw_free_recv_priv
staging: vt6656: Removed unused variable vt3342_vnt_threshold
staging: vt6656: Removed unused variable bb_vga_0
staging: remove ashmem
...
|
||
|
Linus Torvalds
|
02e2af20f4 |
Char/Misc and other driver updates for 5.18-rc1
Here is the big set of char/misc and other small driver subsystem updates for 5.18-rc1. Included in here are merges from driver subsystems which contain: - iio driver updates and new drivers - fsi driver updates - fpga driver updates - habanalabs driver updates and support for new hardware - soundwire driver updates and new drivers - phy driver updates and new drivers - coresight driver updates - icc driver updates Individual changes include: - mei driver updates - interconnect driver updates - new PECI driver subsystem added - vmci driver updates - lots of tiny misc/char driver updates There will be two merge conflicts with your tree, one in MAINTAINERS which is obvious to fix up, and one in drivers/phy/freescale/Kconfig which also should be easy to resolve. All of these have been in linux-next for a while with no reported problems. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> -----BEGIN PGP SIGNATURE----- iG0EABECAC0WIQT0tgzFv3jCIUoxPcsxR9QN2y37KQUCYkG3fQ8cZ3JlZ0Brcm9h aC5jb20ACgkQMUfUDdst+ykNEgCfaRG8CRxewDXOO4+GSeA3NGK+AIoAnR89donC R4bgCjfg8BWIBcVVXg3/ =WWXC -----END PGP SIGNATURE----- Merge tag 'char-misc-5.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc Pull char/misc and other driver updates from Greg KH: "Here is the big set of char/misc and other small driver subsystem updates for 5.18-rc1. Included in here are merges from driver subsystems which contain: - iio driver updates and new drivers - fsi driver updates - fpga driver updates - habanalabs driver updates and support for new hardware - soundwire driver updates and new drivers - phy driver updates and new drivers - coresight driver updates - icc driver updates Individual changes include: - mei driver updates - interconnect driver updates - new PECI driver subsystem added - vmci driver updates - lots of tiny misc/char driver updates All of these have been in linux-next for a while with no reported problems" * tag 'char-misc-5.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (556 commits) firmware: google: Properly state IOMEM dependency kgdbts: fix return value of __setup handler firmware: sysfb: fix platform-device leak in error path firmware: stratix10-svc: add missing callback parameter on RSU arm64: dts: qcom: add non-secure domain property to fastrpc nodes misc: fastrpc: Add dma handle implementation misc: fastrpc: Add fdlist implementation misc: fastrpc: Add helper function to get list and page misc: fastrpc: Add support to secure memory map dt-bindings: misc: add fastrpc domain vmid property misc: fastrpc: check before loading process to the DSP misc: fastrpc: add secure domain support dt-bindings: misc: add property to support non-secure DSP misc: fastrpc: Add support to get DSP capabilities misc: fastrpc: add support for FASTRPC_IOCTL_MEM_MAP/UNMAP misc: fastrpc: separate fastrpc device from channel context dt-bindings: nvmem: brcm,nvram: add basic NVMEM cells dt-bindings: nvmem: make "reg" property optional nvmem: brcm_nvram: parse NVRAM content into NVMEM cells nvmem: dt-bindings: Fix the error of dt-bindings check ... |
||
|
Ansuel Smith
|
887646c47d |
dt-bindings: reset: add ipq8064 ce5 resets
Add ipq8064 ce5 resets needed for CryptoEngine gcc driver. Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Tested-by: Jonathan McDowell <noodles@earth.li> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220226135235.10051-14-ansuelsmth@gmail.com |
||
|
Robert Marko
|
440c7317e4 |
dt-bindings: reset: Add Delta TN48M
Add header for the Delta TN48M CPLD provided resets. Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Robert Marko <robert.marko@sartura.hr> Link: https://lore.kernel.org/r/20220131133049.77780-4-robert.marko@sartura.hr Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
||
|
Vidya Sagar
|
d06a171e07 |
dt-bindings: Add Tegra234 PCIe clocks and resets
Add the clocks and resets used by the PCIe hardware found on Tegra234 SoCs. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com> |
||
|
Mohan Kumar
|
07d743902a |
dt-bindings: Add HDA support for Tegra234
Add hda clocks, memory ,power and reset binding entries for Tegra234. Signed-off-by: Mohan Kumar <mkumard@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> |
||
|
Akhil R
|
38eb21a5fc |
dt-bindings: Add headers for Tegra234 PWM
Add dt-bindings header files for PWM of Tegra234 Signed-off-by: Akhil R <akhilrajeev@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> |
||
|
Akhil R
|
bb747becf8 |
dt-bindings: Add headers for Tegra234 I2C
Add dt-bindings header files for I2C controllers for Tegra234 Signed-off-by: Akhil R <akhilrajeev@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> |
||
|
Sergio Paracuellos
|
f383b07706 |
dt-bindings: reset: add dt binding header for Mediatek MT7621 resets
Add dt binding header for resets lines in Mediatek MT7621 SoCs. Acked-by: Rob Herring <robh@kernel.org> Tested-by: Arınç ÜNAL <arinc.unal@arinc9.com> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20220110114930.1406665-2-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
||
|
Linus Torvalds
|
455e73a07f |
We have a couple patches in the framework core this time around but
they're mostly minor cleanups and some debugfs stuff. The real work
that's in here is the typical pile of clk driver updates and new SoC
support. Per usual (or maybe just recent trends), Qualcomm gains a
handful of SoC drivers additions and has the largest diffstat. After
that there are quite a few updates to the Allwinner (sunxi) drivers to
support modular drivers and Renesas is heavily updated to add more
support for various clks. Overall it looks pretty normal.
New Drivers:
- Add MDMA and BDMA clks to Ingenic JZ4760 and JZ4770
- MediaTek mt7986 SoC basic support
- Clock and reset driver for Toshiba Visconti SoCs
- Initial clock driver for the Exynos7885 SoC (Samsung Galaxy A8)
- Allwinner D1 clks
- Lan966x Generic Clock Controller driver and associated DT bindings
- Qualcomm SDX65, SM8450, and MSM8976 GCC clks
- Qualcomm SDX65 and SM8450 RPMh clks
Updates:
- Set suppress_bind_attrs to true for i.MX8ULP driver
- Switch from do_div to div64_ul for throughout all i.MX drivers
- Fix imx8mn_clko1_sels for i.MX8MN
- Remove unused IPG_AUDIO_ROOT from i.MX8MP
- Switch parent for audio_root_clk to audio ahb in i.MX8MP driver
- Removal of all remaining uses of __clk_lookup() in drivers/clk/samsung
- Refactoring of the CPU clocks registration to use common interface
- An update of the Exynos850 driver (support for more clock domains)
required by the E850-96 development board
- Prep for runtime PM and generic power domains on Tegra
- Support modular Allwinner clk drivers via platform bus
- Lan966x clock driver extended to support clock gating
- Add serial (SCI1), watchdog (WDT), timer (OSTM), SPI (RSPI), and
thermal (TSU) clocks and resets on Renesas RZ/G2L
- Rework SDHI clock handling in the Renesas R-Car Gen3 and RZ/G2 clock
drivers, and in the Renesas SDHI driver
- Make the Cortex-A55 (I) clock on Renesas RZ/G2L programmable
- Document support for the new Renesas R-Car S4-8 (R8A779F0) SoC
- Add support for the new Renesas R-Car S4-8 (R8A779F0) SoC
- Add GPU clock and resets on Renesas RZ/G2L
- Add clk-provider.h to various Qualcomm clk drivers
- devm version of clk_hw_register_gate()
- kerneldoc fixes in a couple drivers
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"We have a couple patches in the framework core this time around but
they're mostly minor cleanups and some debugfs stuff. The real work
that's in here is the typical pile of clk driver updates and new SoC
support.
Per usual (or maybe just recent trends), Qualcomm gains a handful of
SoC drivers additions and has the largest diffstat. After that there
are quite a few updates to the Allwinner (sunxi) drivers to support
modular drivers and Renesas is heavily updated to add more support for
various clks.
Overall it looks pretty normal.
New Drivers:
- Add MDMA and BDMA clks to Ingenic JZ4760 and JZ4770
- MediaTek mt7986 SoC basic support
- Clock and reset driver for Toshiba Visconti SoCs
- Initial clock driver for the Exynos7885 SoC (Samsung Galaxy A8)
- Allwinner D1 clks
- Lan966x Generic Clock Controller driver and associated DT bindings
- Qualcomm SDX65, SM8450, and MSM8976 GCC clks
- Qualcomm SDX65 and SM8450 RPMh clks
Updates:
- Set suppress_bind_attrs to true for i.MX8ULP driver
- Switch from do_div to div64_ul for throughout all i.MX drivers
- Fix imx8mn_clko1_sels for i.MX8MN
- Remove unused IPG_AUDIO_ROOT from i.MX8MP
- Switch parent for audio_root_clk to audio ahb in i.MX8MP driver
- Removal of all remaining uses of __clk_lookup() in
drivers/clk/samsung
- Refactoring of the CPU clocks registration to use common interface
- An update of the Exynos850 driver (support for more clock domains)
required by the E850-96 development board
- Prep for runtime PM and generic power domains on Tegra
- Support modular Allwinner clk drivers via platform bus
- Lan966x clock driver extended to support clock gating
- Add serial (SCI1), watchdog (WDT), timer (OSTM), SPI (RSPI), and
thermal (TSU) clocks and resets on Renesas RZ/G2L
- Rework SDHI clock handling in the Renesas R-Car Gen3 and RZ/G2
clock drivers, and in the Renesas SDHI driver
- Make the Cortex-A55 (I) clock on Renesas RZ/G2L programmable
- Document support for the new Renesas R-Car S4-8 (R8A779F0) SoC
- Add support for the new Renesas R-Car S4-8 (R8A779F0) SoC
- Add GPU clock and resets on Renesas RZ/G2L
- Add clk-provider.h to various Qualcomm clk drivers
- devm version of clk_hw_register_gate()
- kerneldoc fixes in a couple drivers"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (131 commits)
clk: visconti: Remove pointless NULL check in visconti_pll_add_lookup()
clk: mediatek: add mt7986 clock support
clk: mediatek: add mt7986 clock IDs
dt-bindings: clock: mediatek: document clk bindings for mediatek mt7986 SoC
clk: mediatek: clk-gate: Use regmap_{set/clear}_bits helpers
clk: mediatek: clk-gate: Shrink by adding clockgating bit check helper
clk: x86: Fix clk_gate_flags for RV_CLK_GATE
clk: x86: Use dynamic con_id string during clk registration
ACPI: APD: Add a fmw property clk-name
drivers: acpi: acpi_apd: Remove unused device property "is-rv"
x86: clk: clk-fch: Add support for newer family of AMD's SOC
clk: ingenic: Add MDMA and BDMA clocks
dt-bindings: clk/ingenic: Add MDMA and BDMA clocks
clk: bm1880: remove kfrees on static allocations
clk: Drop unused COMMON_CLK_STM32MP157_SCMI config
clk: st: clkgen-mux: search reg within node or parent
clk: st: clkgen-fsyn: search reg within node or parent
clk: Enable/Disable runtime PM for clk_summary
MAINTAINERS: Add entries for Toshiba Visconti PLL and clock controller
clk: visconti: Add support common clock driver and reset driver
...
|
||
|
Stephen Boyd
|
1d0bd126d9 |
Merge branches 'clk-socfpga', 'clk-toshiba', 'clk-st' and 'clk-bitmain' into clk-next
- Clock and reset driver for Toshiba Visconti SoCs * clk-socfpga: clk: socfpga: s10: Make use of the helper function devm_platform_ioremap_resource() clk: socfpga: agilex: Make use of the helper function devm_platform_ioremap_resource() clk: socfpga: remove redundant assignment after a mask operation clk: socfpga: remove redundant assignment on division * clk-toshiba: clk: visconti: Remove pointless NULL check in visconti_pll_add_lookup() MAINTAINERS: Add entries for Toshiba Visconti PLL and clock controller clk: visconti: Add support common clock driver and reset driver dt-bindings: clock: Add DT bindings for SMU of Toshiba Visconti TMPV770x SoC dt-bindings: clock: Add DT bindings for PLL of Toshiba Visconti TMPV770x SoC * clk-st: clk: Drop unused COMMON_CLK_STM32MP157_SCMI config clk: st: clkgen-mux: search reg within node or parent clk: st: clkgen-fsyn: search reg within node or parent * clk-bitmain: clk: bm1880: remove kfrees on static allocations |
||
|
Linus Torvalds
|
bb4ed26e7e |
SoC: Add support for StarFive JH7100 RISC-V SoC
This adds support for the StarFive JH7100, including the necessary device drivers and DT files for the BeagleV Starlight prototype board, with additional boards to be added later. This SoC promises to be the first usable low-cost platform for RISC-V. I've taken this through the SoC tree in the anticipation of adding a few other Arm based SoCs as well, but those did not pass the review in time, so it's only this one. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmHE4/wACgkQmmx57+YA GNlSlRAArOIWkgB8Uwf2dz1tdyGNo6b0yqrqPBnc2hlafQVkrd/Cy0imIEt21pJk IkVviuuJmWMS7lFppvjoKbTZDvGt4gcA2o//NorBtSLV5G7mbJAMkeDtfdURRAb0 c7IXbtHaI5qMPHXOzjbKTHedbLJpS2P1uXQtGr9hiZFP8ZfyfbEF1bzL0edcCAWi DuY7cpEHEzeKATN8NQ1ETwpx0MJBfp7pzyfQbB9I1VvIMX1qbuLBUUJ6snLGSiw1 kvLrQoV+2ZISeEfQ8M/PoHpHexO7CzY0thlTFt2mThLVI0ZlaVJvI6oJDAX5AG67 tsmDiBxzvp+gWx5T8TfCgETJOVPUpNpSodF8U+cvIIpZM+DLiDc3Dyu6Zrod5guZ y989Sc+Be1LZEEyy0VscCoDleNxuFohh8aNJZnRtzd5UfJnz7cDIfGUdS2hwP9JN vI7Ci4nQIcvG35RwnLVMOp1azm3RIv2xoESdLkbS9/4smNEjLT1xtr6uVcP+MIKE qsWh8TITRWF4aiFqmsz1JyTHFAL0cCi4lZM//Y6XGKM2z0sCmpbfHIEGhJWuSNme lXvqn62VfiA5CvSnijYMwtRnCKIDDhsjvQo6H0gxCqW6ynCnKAivL/yo65hqtQO8 wBpmlziU7IXx4Js/1eGpF7zq7a9LHFqFnKCrE/+7hK/DPGF2Qck= =X5uk -----END PGP SIGNATURE----- Merge tag 'newsoc-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull RISC-V SoC updates from Arnd Bergmann: "Add support for StarFive JH7100 RISC-V SoC This adds support for the StarFive JH7100, including the necessary device drivers and DT files for the BeagleV Starlight prototype board, with additional boards to be added later. This SoC promises to be the first usable low-cost platform for RISC-V. I've taken this through the SoC tree in the anticipation of adding a few other Arm based SoCs as well, but those did not pass the review in time, so it's only this one" * tag 'newsoc-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: reset: starfive-jh7100: Fix 32bit compilation RISC-V: Add BeagleV Starlight Beta device tree RISC-V: Add initial StarFive JH7100 device tree serial: 8250_dw: Add StarFive JH7100 quirk dt-bindings: serial: snps-dw-apb-uart: Add JH7100 uarts pinctrl: starfive: Add pinctrl driver for StarFive SoCs dt-bindings: pinctrl: Add StarFive JH7100 bindings dt-bindings: pinctrl: Add StarFive pinctrl definitions reset: starfive-jh7100: Add StarFive JH7100 reset driver dt-bindings: reset: Add Starfive JH7100 reset bindings dt-bindings: reset: Add StarFive JH7100 reset definitions clk: starfive: Add JH7100 clock generator driver dt-bindings: clock: starfive: Add JH7100 bindings dt-bindings: clock: starfive: Add JH7100 clock definitions dt-bindings: interrupt-controller: Add StarFive JH7100 plic dt-bindings: timer: Add StarFive JH7100 clint RISC-V: Add StarFive SoC Kconfig option |
||
|
Nobuhiro Iwamatsu
|
ffa81a0326 |
dt-bindings: clock: Add DT bindings for SMU of Toshiba Visconti TMPV770x SoC
Add device tree bindings for SMU (System Management Unit) controller of Toshiba Visconti TMPV770x SoC series. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20211025031038.4180686-3-nobuhiro1.iwamatsu@toshiba.co.jp Signed-off-by: Stephen Boyd <sboyd@kernel.org> |
||
|
Geert Uytterhoeven
|
810e287e83 |
dt-bindings: reset: Add StarFive JH7100 reset definitions
Add all resets for the StarFive JH7100 reset controller. Based on work by Ahmad Fatoum for Barebox, with "JH7100_" prefixes added to all definitions. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> |
||
|
Mikko Perttunen
|
fc5e0e3762 |
dt-bindings: Update headers for Tegra234
Add a few more clocks that will be used in follow-up patches to enable more functionality on Tegra234. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com> |
||
|
Samuel Holland
|
c962f10f39
|
dt-bindings: clk: Add compatibles for D1 CCUs
The D1 has a CCU and a R_CCU (PRCM CCU) like most other sunxi SoCs, with 3 and 4 clock inputs, respectively. Add the compatibles and bindings. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20211119043545.4010-2-samuel@sholland.org |
||
|
Linus Torvalds
|
7ddb58cb0e |
The usual collection of clk driver updates and new driver additions. In
terms of lines it's mainly Qualcomm and Mediatek code, supporting
various SoCs and their multitude of clk controllers.
New Drivers:
- GCC and RPMcc support for Qualcomm QCM2290 SoCs
- GCC support for Qualcomm MSM8994/MSM8992 SoCs
- LPASSCC and CAMCC support for Qualcomm SC7280 SoCs
- Support for Mediatek MT8195 SoCs
- Initial clock driver for the Exynos850 SoC
- Add i.MX8ULP clock driver and related bindings
Updates:
- Clock power management for new SAMA7G5 SoC
- Updates to the master clock driver and sam9x60-pll to be able to use
cpufreq-dt driver and avoid overclocking of CPU and MCK0 domains while
changing the frequency via DVFS
- Use ARRAY_SIZE in qcom clk drivers
- Remove some impractical fallback parent names in qcom clk drivers
- Make Mediatek clk drivers tristate
- Refactoring of the CPU clock code and conversion of Samsung Exynos5433
CPU clock driver to the platform driver
- A few conversions to devm_platform_ioremap_resource()
- Updates of the Samsung Kconfig help text
- Update video path realted clocks for Amlogic meson8
- Add SPI Multi I/O Bus and SDHI clocks and resets on Renesas RZ/G2L
- Add SPI Multi I/O Bus (RPC) clocks on Renesas R-Car V3U
- Add MediaLB clocks on Renesas R-Car H3, M3-W/W+, and M3-N
- Remove unused helpers from i.MX specific clock header
- Rework all i.MX clk based helpers to use clk_hw based ones
- Rework i.MX gate/mux/divider wrappers
- Rework imx_clk_hw_composite and imx_clk_hw_pll14xx wrappers
- Update i.MX pllv4 and composite clocks to support i.MX8ULP
- Disable i.MX7ULP composite clock during initialization
- Add CLK_SET_RATE_NO_REPARENT flag to the i.MX7ULP composite
- Disable the i.MX pfd when set pfdv2 clock rate
- Add support for i.MX8ULP in pfdv2
- Add the pcc reset controller support on i.MX8ULP
- Fix the build break when clk-imx8ulp is built as module
- Move csi_sel mux to correct base register in i.MX6UL clock drivr
- Fix csi clk gate register in i.MX6UL clock driver
- Fix build bug making CLK_IMX8ULP select MXC_CLK
- Add TPU (PWM), and Z (Cortex-A76) clocks on Renesas R-Car V3U
- Add Ethernet clocks on Renesas RZ/G2L
- Move Rockchip to use module_platform_probe
- Enable usage of Coresight related clocks on Rockchip rk3399
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"The usual collection of clk driver updates and new driver additions.
In terms of lines it's mainly Qualcomm and Mediatek code, supporting
various SoCs and their multitude of clk controllers.
New Drivers:
- GCC and RPMcc support for Qualcomm QCM2290 SoCs
- GCC support for Qualcomm MSM8994/MSM8992 SoCs
- LPASSCC and CAMCC support for Qualcomm SC7280 SoCs
- Support for Mediatek MT8195 SoCs
- Initial clock driver for the Exynos850 SoC
- Add i.MX8ULP clock driver and related bindings
Updates:
- Clock power management for new SAMA7G5 SoC
- Updates to the master clock driver and sam9x60-pll to be able to
use cpufreq-dt driver and avoid overclocking of CPU and MCK0
domains while changing the frequency via DVFS
- Use ARRAY_SIZE in qcom clk drivers
- Remove some impractical fallback parent names in qcom clk drivers
- Make Mediatek clk drivers tristate
- Refactoring of the CPU clock code and conversion of Samsung
Exynos5433 CPU clock driver to the platform driver
- A few conversions to devm_platform_ioremap_resource()
- Updates of the Samsung Kconfig help text
- Update video path realted clocks for Amlogic meson8
- Add SPI Multi I/O Bus and SDHI clocks and resets on Renesas RZ/G2L
- Add SPI Multi I/O Bus (RPC) clocks on Renesas R-Car V3U
- Add MediaLB clocks on Renesas R-Car H3, M3-W/W+, and M3-N
- Remove unused helpers from i.MX specific clock header
- Rework all i.MX clk based helpers to use clk_hw based ones
- Rework i.MX gate/mux/divider wrappers
- Rework imx_clk_hw_composite and imx_clk_hw_pll14xx wrappers
- Update i.MX pllv4 and composite clocks to support i.MX8ULP
- Disable i.MX7ULP composite clock during initialization
- Add CLK_SET_RATE_NO_REPARENT flag to the i.MX7ULP composite
- Disable the i.MX pfd when set pfdv2 clock rate
- Add support for i.MX8ULP in pfdv2
- Add the pcc reset controller support on i.MX8ULP
- Fix the build break when clk-imx8ulp is built as module
- Move csi_sel mux to correct base register in i.MX6UL clock drivr
- Fix csi clk gate register in i.MX6UL clock driver
- Fix build bug making CLK_IMX8ULP select MXC_CLK
- Add TPU (PWM), and Z (Cortex-A76) clocks on Renesas R-Car V3U
- Add Ethernet clocks on Renesas RZ/G2L
- Move Rockchip to use module_platform_probe
- Enable usage of Coresight related clocks on Rockchip rk3399"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (170 commits)
clk: use clk_core_get_rate_recalc() in clk_rate_get()
clk: at91: sama7g5: set low limit for mck0 at 32KHz
clk: at91: sama7g5: remove prescaler part of master clock
clk: at91: clk-master: add notifier for divider
clk: at91: clk-sam9x60-pll: add notifier for div part of PLL
clk: at91: clk-master: fix prescaler logic
clk: at91: clk-master: mask mckr against layout->mask
clk: at91: clk-master: check if div or pres is zero
clk: at91: sam9x60-pll: use DIV_ROUND_CLOSEST_ULL
clk: at91: pmc: add sama7g5 to the list of available pmcs
clk: at91: clk-master: improve readability by using local variables
clk: at91: clk-master: add register definition for sama7g5's master clock
clk: at91: sama7g5: add securam's peripheral clock
clk: at91: pmc: execute suspend/resume only for backup mode
clk: at91: re-factor clocks suspend/resume
clk: ux500: Add driver for the reset portions of PRCC
dt-bindings: clock: u8500: Rewrite in YAML and extend
clk: composite: Use rate_ops.determine_rate when also a mux is available
clk: samsung: describe drivers in Kconfig
clk: samsung: exynos5433: update apollo and atlas clock probing
...
|
||
|
Stephen Boyd
|
8d741ecd46 |
Merge branches 'clk-imx', 'clk-ux500' and 'clk-debugfs' into clk-next
* clk-imx: (21 commits) clk: imx: Make CLK_IMX8ULP select MXC_CLK clk: imx: imx6ul: Fix csi clk gate register clk: imx: imx6ul: Move csi_sel mux to correct base register clk: imx: Fix the build break when clk-imx8ulp build as module clk: imx: Add the pcc reset controller support on imx8ulp clk: imx: Add clock driver for imx8ulp clk: imx: Update the pfdv2 for 8ulp specific support clk: imx: disable the pfd when set pfdv2 clock rate clk: imx: Add 'CLK_SET_RATE_NO_REPARENT' for composite-7ulp clk: imx: disable i.mx7ulp composite clock during initialization clk: imx: Update the compsite driver to support imx8ulp clk: imx: Update the pllv4 to support imx8ulp dt-bindings: clock: Add imx8ulp clock support clk: imx: Rework imx_clk_hw_pll14xx wrapper clk: imx: Rework all imx_clk_hw_composite wrappers clk: imx: Rework all clk_hw_register_divider wrappers clk: imx: Rework all clk_hw_register_mux wrappers clk: imx: Rework all clk_hw_register_gate2 wrappers clk: imx: Rework all clk_hw_register_gate wrappers clk: imx: Make mux/mux2 clk based helpers use clk_hw based ones ... * clk-ux500: clk: ux500: Add driver for the reset portions of PRCC dt-bindings: clock: u8500: Rewrite in YAML and extend * clk-debugfs: clk: use clk_core_get_rate_recalc() in clk_rate_get() |
||
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Linus Walleij
|
f2b883bbdd |
dt-bindings: clock: u8500: Rewrite in YAML and extend
This rewrites the ux500/u8500 clock bindings in YAML schema and extends them with the PRCC reset controller. The bindings are a bit idiomatic but it just reflects their age, the ux500 platform was used as guinea pig for early device tree conversion of platforms in 2015. The new subnode for the reset controller follows the pattern of the old bindings and adds a node with reset-cells for this. Cc: devicetree@vger.kernel.org Cc: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20210921184803.1757916-1-linus.walleij@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org> |
||
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Enric Balletbo i Serra
|
4bdb00edbd |
arm64: dts: mt8183: Add the mmsys reset bit to reset the dsi0
Reset the DSI hardware is needed to prevent different settings between the bootloader and the kernel. While here, also remove the undocumented and also not used 'mediatek,syscon-dsi' property. Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210930103105.v4.5.I933f1532d7a1b2910843a9644c86a7d94a4b44e1@changeid Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> |
||
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Enric Balletbo i Serra
|
7fdb1bc3d9 |
arm64: dts: mt8173: Add the mmsys reset bit to reset the dsi0
Reset the DSI hardware is needed to prevent different settings between the bootloader and the kernel. Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210930103105.v4.4.I7bd7d9a8da5e2894711b700a1127e6902a2b2f1d@changeid Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> |
||
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Enric Balletbo i Serra
|
f07c776f6d |
arm64: dts: mediatek: Move reset controller constants into common location
The DT binding includes for reset controllers are located in include/dt-bindings/reset/. Move the Mediatek reset constants in there. Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Link: https://lore.kernel.org/r/20210930103105.v4.1.I514d9aafff3a062f751b37d3fea7402f67595b86@changeid Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> |
||
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Jacky Bai
|
d48f12d9ae |
dt-bindings: clock: Add imx8ulp clock support
Add the clock dt-binding file for i.MX8ULP. For pcc node, it will also be used as a reset controller, so add the '#reset-cells' property description and add the pcc reset IDs. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20210914065208.3582128-2-ping.bai@nxp.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com> |
||
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Linus Torvalds
|
4c00e1e2e5 |
linux-watchdog 5.15-rc1 tag
-----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.14 (GNU/Linux) iEYEABECAAYFAmE3t2UACgkQ+iyteGJfRspKrgCfVDZuMeFiDrRjPz9FMDUncIZ7 /24AoKWWPcOJLNXXNCwwD61kcW34LzVV =gMcs -----END PGP SIGNATURE----- Merge tag 'linux-watchdog-5.15-rc1' of git://www.linux-watchdog.org/linux-watchdog Pull watchdog updates from Wim Van Sebroeck: - add Mediatek MT7986 & MT8195 wdt support - add Maxim MAX63xx - drop bd70528 support - rewrite ixp4xx to watchdog framework - constify static struct watchdog_ops for sl28cpld_wdt, mpc8xxx_wdt and tqmx86 - introduce watchdog_dev_suspend/resume - several fixes and improvements * tag 'linux-watchdog-5.15-rc1' of git://www.linux-watchdog.org/linux-watchdog: dt-bindings: watchdog: Add compatible for Mediatek MT7986 watchdog: ixp4xx: Rewrite driver to use core watchdog: Start watchdog in watchdog_set_last_hw_keepalive only if appropriate watchdog: max63xx_wdt: Add device tree probing dt-bindings: watchdog: Add Maxim MAX63xx bindings watchdog: mediatek: mt8195: add wdt support dt-bindings: reset: mt8195: add toprgu reset-controller header file watchdog: tqmx86: Constify static struct watchdog_ops watchdog: mpc8xxx_wdt: Constify static struct watchdog_ops watchdog: sl28cpld_wdt: Constify static struct watchdog_ops watchdog: iTCO_wdt: Fix detection of SMI-off case watchdog: bcm2835_wdt: consider system-power-controller property watchdog: imx2_wdg: notify wdog core to stop ping worker on suspend watchdog: introduce watchdog_dev_suspend/resume watchdog: Fix NULL pointer dereference when releasing cdev watchdog: only run driver set_pretimeout op if device supports it watchdog: bd70528 drop bd70528 support |
||
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Christine Zhu
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39c5b2f6f2 |
dt-bindings: reset: mt8195: add toprgu reset-controller header file
Add toprgu reset-controller header file for MT8195 platform. Signed-off-by: Christine Zhu <Christine.Zhu@mediatek.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Link: https://lore.kernel.org/r/20210726122901.12195-3-Christine.Zhu@mediatek.com Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org> |
||
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Sibi Sankar
|
9e3b594a92 |
dt-bindings: reset: pdc: Add PDC Global bindings
Add PDC Global reset controller bindings for SC7280 SoCs. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Link: https://lore.kernel.org/r/1619693465-5724-4-git-send-email-sibis@codeaurora.org Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> |
||
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Gabriel Fernandez
|
f040e135c5 |
dt-bindings: reset: add MCU HOLD BOOT ID for SCMI reset domains on stm32mp15
Add ID to SCMI0 to exposes reset controller for the MCU HOLD BOOT resource. Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210617051814.12018-10-gabriel.fernandez@foss.st.com Signed-off-by: Stephen Boyd <sboyd@kernel.org> |
||
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Gabriel Fernandez
|
256c7521cb |
dt-bindings: reset: add IDs for SCMI reset domains on stm32mp15
stm32mp15 TZ secure firmware provides SCMI reset domains for secure resources. This change defines the SCMI reset domain identifiers used by SCMI agents and servers. Stm32mp15 TZ secure firmware provides SCMI clocks for oscillators, some PLL output and few secure aware interfaces. This change defines the SCMI clock identifiers used by SCMI agents and servers. Server SCMI0 exposes reset controllers for resources under RCC[TZEN] configuration control. Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210617051814.12018-9-gabriel.fernandez@foss.st.com Signed-off-by: Stephen Boyd <sboyd@kernel.org> |
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Linus Torvalds
|
8b83369ddc |
RISC-V Patches for the 5.12 Merge Window
I have a handful of new RISC-V related patches for this merge window:
* A check to ensure drivers are properly using uaccess. This isn't
manifesting with any of the drivers I'm currently using, but may catch
errors in new drivers.
* Some preliminary support for the FU740, along with the HiFive
Unleashed it will appear on.
* NUMA support for RISC-V, which involves making the arm64 code generic.
* Support for kasan on the vmalloc region.
* A handful of new drivers for the Kendryte K210, along with the DT
plumbing required to boot on a handful of K210-based boards.
* Support for allocating ASIDs.
* Preliminary support for kernels larger than 128MiB.
* Various other improvements to our KASAN support, including the
utilization of huge pages when allocating the KASAN regions.
We may have already found a bug with the KASAN_VMALLOC code, but it's
passing my tests. There's a fix in the works, but that will probably
miss the merge window.
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Merge tag 'riscv-for-linus-5.12-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull RISC-V updates from Palmer Dabbelt:
"A handful of new RISC-V related patches for this merge window:
- A check to ensure drivers are properly using uaccess. This isn't
manifesting with any of the drivers I'm currently using, but may
catch errors in new drivers.
- Some preliminary support for the FU740, along with the HiFive
Unleashed it will appear on.
- NUMA support for RISC-V, which involves making the arm64 code
generic.
- Support for kasan on the vmalloc region.
- A handful of new drivers for the Kendryte K210, along with the DT
plumbing required to boot on a handful of K210-based boards.
- Support for allocating ASIDs.
- Preliminary support for kernels larger than 128MiB.
- Various other improvements to our KASAN support, including the
utilization of huge pages when allocating the KASAN regions.
We may have already found a bug with the KASAN_VMALLOC code, but it's
passing my tests. There's a fix in the works, but that will probably
miss the merge window.
* tag 'riscv-for-linus-5.12-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (75 commits)
riscv: Improve kasan population by using hugepages when possible
riscv: Improve kasan population function
riscv: Use KASAN_SHADOW_INIT define for kasan memory initialization
riscv: Improve kasan definitions
riscv: Get rid of MAX_EARLY_MAPPING_SIZE
soc: canaan: Sort the Makefile alphabetically
riscv: Disable KSAN_SANITIZE for vDSO
riscv: Remove unnecessary declaration
riscv: Add Canaan Kendryte K210 SD card defconfig
riscv: Update Canaan Kendryte K210 defconfig
riscv: Add Kendryte KD233 board device tree
riscv: Add SiPeed MAIXDUINO board device tree
riscv: Add SiPeed MAIX GO board device tree
riscv: Add SiPeed MAIX DOCK board device tree
riscv: Add SiPeed MAIX BiT board device tree
riscv: Update Canaan Kendryte K210 device tree
dt-bindings: add resets property to dw-apb-timer
dt-bindings: fix sifive gpio properties
dt-bindings: update sifive uart compatible string
dt-bindings: update sifive clint compatible string
...
|
||
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Andre Przywara
|
88dde5e23d
|
clk: sunxi-ng: Add support for the Allwinner H616 CCU
While the clocks are fairly similar to the H6, many differ in tiny details, so a separate clock driver seems indicated. Derived from the H6 clock driver, and adjusted according to the manual. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20210127172500.13356-4-andre.przywara@arm.com |
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Damien Le Moal
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1d7c9d093e
|
dt-bindings: reset: Document canaan,k210-rst bindings
Document the device tree bindings for the Canaan Kendryte K210 SoC reset controller driver in Documentation/devicetree/bindings/reset/canaan,k210-rst.yaml. The header file include/dt-bindings/reset/k210-rst.h is added to define all possible reset lines of the SoC. Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
||
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Samuel Holland
|
0482a4e6de |
clk: sunxi-ng: h6-r: Add R_APB2_RSB clock and reset
While no information about the H6 RSB controller is included in the datasheet or manual, the vendor BSP and power management blob both reference the RSB clock parent and register address. These values were verified by experimentation. Since this clock/reset are added late, the specifier is added at the end to maintain the existing DT binding. The code is kept in register order. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Chen-Yu Tsai <wens@csie.org> |
||
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Álvaro Fernández Rojas
|
8c9e8b0a28 |
mips: bmips: add BCM6318 reset controller definitions
BCM6318 SoCs have a reset controller for certain components. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Acked-by: Florian Fainelli <F.fainelli@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> |
||
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Álvaro Fernández Rojas
|
b7aa228813 |
mips: bmips: dts: add BCM63268 reset controller support
BCM63268 SoCs have a reset controller for certain components. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> |
||
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Álvaro Fernández Rojas
|
7acf84e878 |
mips: bmips: dts: add BCM6368 reset controller support
BCM6368 SoCs have a reset controller for certain components. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> |
||
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Álvaro Fernández Rojas
|
226383600b |
mips: bmips: dts: add BCM6362 reset controller support
BCM6362 SoCs have a reset controller for certain components. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> |
||
|
Álvaro Fernández Rojas
|
8079cfba4c |
mips: bmips: dts: add BCM6358 reset controller support
BCM6358 SoCs have a reset controller for certain components. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> |
||
|
Álvaro Fernández Rojas
|
83f865d7e3 |
mips: bmips: dts: add BCM6328 reset controller support
BCM6328 SoCs have a reset controller for certain components. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> |
||
|
Linus Torvalds
|
e533cda12d |
ARM: Devicetree updates
As usual, most of the changes are to devicetrees. Besides smaller fixes, some refactorings and cleanups, some of the new platforms and chips (or significant features) supported are below: Broadcom boards: - Cisco Meraki MR32 (BCM53016-based) - BCM2711 (RPi4) display pipeline support Actions Semi boards: - Caninos Loucos Labrador SBC (S500-based) - RoseapplePi SBC (S500-based) Allwinner SoCs/boards: - A100 SoC with Perf1 board - Mali, DMA, Cetrus and IR support for R40 SoC Amlogic boards: - Libretch S905x CC V2 board - Hardkernel ODROID-N2+ board Aspeed boards/platforms: - Wistron Mowgli (AST2500-based, Power9 OpenPower server) - Facebook Wedge400 (AST2500-based, ToR switch) Hisilicon SoC: - SD5203 SoC Nvidia boards: - Tegra234 VDK, for pre-silicon Orin SoC NXP i.MX boards: - Librem 5 phone - i.MX8MM DDR4 EVK - Variscite VAR-SOM-MX8MN SoM - Symphony board - Tolino Shine 2 HD - TQMa6 SoM - Y Soft IOTA Orion Rockchip boards: - NanoPi R2S board - A95X-Z2 board - more Rock-Pi4 variants STM32 boards: - Odyssey SOM board (STM32MP157CAC-based) - DH DRC02 board Toshiba SoCs/boards: - Visconti SoC and TPMV7708 board -----BEGIN PGP SIGNATURE----- iQJDBAABCgAtFiEElf+HevZ4QCAJmMQ+jBrnPN6EHHcFAl+TVacPHG9sb2ZAbGl4 b20ubmV0AAoJEIwa5zzehBx37MMP/imMO5e0QY1/7xxXWm4Kgc/Uffqw2Dvhj74a 4Nrudwz6oUFGpZzIFYxqeCeWwotjA0nXmvM4Nl/SbxtlbV6nY/JrOL1OJToaGY0z Oc1jdA0MdXITdi6Xl5PTRqDeIHTSUmTclZWi5gvT7LFEvHog3mquJ7PiNTrjyuV0 9BmHipwfmH6V5gDJZvN2dDlkhy0cpQKJFw7ylKCL89UNiEAd2QtNG0d0RLdz7yPX IGdecFelOhG9MSZyuFYYB2HOI33ukjZ9dA+yFy7BWOqegf/Z5hI02mxpke7Sys/5 4XEN7ksSSYr6sm3h9XNW++IYkapZ9y/ZW+sQdiBZ3GMOwMXj02TdRkpC7f+FgAPo Hl7yXodGmXynL6ULu7/lIbBvqfWkLcwfVCYZx6PoWRE2q5g5ifoYp9b8kI5cLXrb BJn85XIuIaoO0cgrq7EzZnksaiwY1CNL84mYgkKRCGbBoJKHRiU+8Ilm5SKzk3kq KJ0gmbwFMjvTYxs3g6LPCo0jUNLjmLQMr0tL7iHDWkk5uqA+gfjKSLQfPby3jrMr 6RDZBzMB+tPz1e++RWo41XD/Mm2kw8MGstsCOLzk2TdLh7e3fPfU4g7m0aqs/Q1y +LCqshffF/XVzV2uTFHDUGWufIM9nY6rdzuBc+JACJ5E+QyDg1tGKtMB3TYqgdN2 aRY3NLSv =xjfB -----END PGP SIGNATURE----- Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM Devicetree updates from Olof Johansson: "As usual, most of the changes are to devicetrees. Besides smaller fixes, some refactorings and cleanups, some of the new platforms and chips (or significant features) supported are below: Broadcom boards: - Cisco Meraki MR32 (BCM53016-based) - BCM2711 (RPi4) display pipeline support Actions Semi boards: - Caninos Loucos Labrador SBC (S500-based) - RoseapplePi SBC (S500-based) Allwinner SoCs/boards: - A100 SoC with Perf1 board - Mali, DMA, Cetrus and IR support for R40 SoC Amlogic boards: - Libretch S905x CC V2 board - Hardkernel ODROID-N2+ board Aspeed boards/platforms: - Wistron Mowgli (AST2500-based, Power9 OpenPower server) - Facebook Wedge400 (AST2500-based, ToR switch) Hisilicon SoC: - SD5203 SoC Nvidia boards: - Tegra234 VDK, for pre-silicon Orin SoC NXP i.MX boards: - Librem 5 phone - i.MX8MM DDR4 EVK - Variscite VAR-SOM-MX8MN SoM - Symphony board - Tolino Shine 2 HD - TQMa6 SoM - Y Soft IOTA Orion Rockchip boards: - NanoPi R2S board - A95X-Z2 board - more Rock-Pi4 variants STM32 boards: - Odyssey SOM board (STM32MP157CAC-based) - DH DRC02 board Toshiba SoCs/boards: - Visconti SoC and TPMV7708 board" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (638 commits) ARM: dts: nspire: Fix SP804 users arm64: dts: lg: Fix SP804 users arm64: dts: lg: Fix SP805 clocks ARM: mstar: Fix up the fallout from moving the dts/dtsi files ARM: mstar: Add mstar prefix to all of the dtsi/dts files ARM: mstar: Add interrupt to pm_uart ARM: mstar: Add interrupt controller to base dtsi ARM: dts: meson8: remove two invalid interrupt lines from the GPU node arm64: dts: ti: k3-j7200-common-proc-board: Add USB support arm64: dts: ti: k3-j7200-common-proc-board: Configure the SERDES lane function arm64: dts: ti: k3-j7200-main: Add USB controller arm64: dts: ti: k3-j7200-main.dtsi: Add USB to SERDES lane MUX arm64: dts: ti: k3-j7200-main: Add SERDES lane control mux dt-bindings: ti-serdes-mux: Add defines for J7200 SoC ARM: dts: hisilicon: add SD5203 dts ARM: dts: hisilicon: fix the system controller compatible nodes arm64: dts: zynqmp: Fix leds subnode name for zcu100/ultra96 v1 arm64: dts: zynqmp: Remove undocumented u-boot properties arm64: dts: zynqmp: Remove additional compatible string for i2c IPs arm64: dts: zynqmp: Rename buses to be align with simple-bus yaml ... |
||
|
Linus Torvalds
|
2e368dd2bb |
ARM: SoC-related driver updates
Various driver updates for platforms. A bulk of this is smaller fixes or cleanups, but some of the new material this time around is: - Support for Nvidia Tegra234 SoC - Ring accelerator support for TI AM65x - PRUSS driver for TI platforms - Renesas support for R-Car V3U SoC - Reset support for Cortex-M4 processor on i.MX8MQ There are also new socinfo entries for a handful of different SoCs and platforms. -----BEGIN PGP SIGNATURE----- iQJDBAABCgAtFiEElf+HevZ4QCAJmMQ+jBrnPN6EHHcFAl+TUboPHG9sb2ZAbGl4 b20ubmV0AAoJEIwa5zzehBx3T4YP/R5pjF2C1gt8FrCaG4IfhIY1VHWelfPcB5qB RC7Pn4MCRCEY+10YPXA70oS6KBaC+gtZ4bPeInzfLXh1ynFJJb+XtAIxoRhnkEw+ /R979wNcIls9JqkvnHWFx29Y008W2ZNcXVNKH7O2Gxy+eKzDcTMsoH/zj8xWrV5b +eBllTzGU4RArYRJdcwOBQwMO6L2pzADHZ7hGMAY//8fo+qrxg8b9EINsH1UHCa8 gQdWdVlmv6GeLB6RYLRBCWxpW4jOLDqEAvyDV84QQmYHvzD9tqJExNR0hfGTs4TU TZWK7LWSNqF0ujQUbFh9Ikcx6DypU1gvE7LKhCDrf4D7HLRX5v4BjGH+xtVtjsyD xzh4WEoa3qCNu1mxQjKG8Y6U7bB9cRI2TPVxbbmI4ZuF0njvybecwwOZUBQl4aD4 5x+Df3pO/E5ECLOBeTnLgvw20fcjHv4HP8l63B6ADb31FUiZrJXItvayY5qXWe+P HSgUykmVA4nd4PnLsSj9seyWqOTIqUZ3U3TsmfxIQh2Otie01okwuHb1J7ErO/u0 W148SgSwVbnkPxjbBHKGgC2r+Q/AjSDGRBYL0ThIVFUztxTBBwhj3FIvMnyyxTIj yFBY14KQ8FcNUs8DrbPCaAx/RDCB02IHdvvIlyTmU3RBq7UhJVIglpLzzo2ed9F2 5u/aVH3y =tfPb -----END PGP SIGNATURE----- Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC-related driver updates from Olof Johansson: "Various driver updates for platforms. A bulk of this is smaller fixes or cleanups, but some of the new material this time around is: - Support for Nvidia Tegra234 SoC - Ring accelerator support for TI AM65x - PRUSS driver for TI platforms - Renesas support for R-Car V3U SoC - Reset support for Cortex-M4 processor on i.MX8MQ There are also new socinfo entries for a handful of different SoCs and platforms" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (131 commits) drm/mediatek: reduce clear event soc: mediatek: cmdq: add clear option in cmdq_pkt_wfe api soc: mediatek: cmdq: add jump function soc: mediatek: cmdq: add write_s_mask value function soc: mediatek: cmdq: add write_s value function soc: mediatek: cmdq: add read_s function soc: mediatek: cmdq: add write_s_mask function soc: mediatek: cmdq: add write_s function soc: mediatek: cmdq: add address shift in jump soc: mediatek: mtk-infracfg: Fix kerneldoc soc: amlogic: pm-domains: use always-on flag reset: sti: reset-syscfg: fix struct description warnings reset: imx7: add the cm4 reset for i.MX8MQ dt-bindings: reset: imx8mq: add m4 reset reset: Fix and extend kerneldoc reset: reset-zynqmp: Added support for Versal platform dt-bindings: reset: Updated binding for Versal reset driver reset: imx7: Support module build soc: fsl: qe: Remove unnessesary check in ucc_set_tdm_rxtx_clk soc: fsl: qman: convert to use be32_add_cpu() ... |
||
|
Linus Torvalds
|
3fec0eaaf0 |
This pull request contains zero diff to the core framework. It is a collection
of various clk driver updates. The biggest driver updates in terms of lines of
code is the Allwinner driver, closely followed by the Qualcomm and Mediatek
drivers. All of those hit high because we add so many lines of clk data. Coming
in fourth place is i.MX which also adds a bunch of clk data. This accounts for
the new driver additions this time around.
Otherwise the patches are lots of little cleanups and fixes for various clk
drivers that have baked in linux-next for a while. I suppose one highlight or
theme is that more clk drivers are being updated to work as modules, which is
interesting to see such critical SoC infrastructure work as a loadable module.
New Drivers:
- Support qcom SM8150/SM8250 video and display clks
- Support Mediatek MT8167 clks
- Add clock for CRC block found on vf610 SoCs
- Add support for the Renesas R-Car V3U (R8A779A0) SoC
- Add support for the VSP for Resizing clock on Renesas RZ/G1H
- Support Allwinner A100 SoC clks
Removed Drivers:
- Remove i.MX21 clock driver, as i.MX21 platform support is being dropped
Updates:
- Change how qcom's display port clks work
- Small non-critical fixes for TI clk driver
- Remove various unused variables in clk drivers
- Allow Rockchip clk driver to be a module
- Remove most __clk_lookup() calls in Samsung drivers (yay!)
- Support building i.MX ARMv8 platforms clock driver as module
- Some kerneldoc fixes here and there
- A couple of minor i.MX clk data corrections
- Update audio clock inverter and fdiv2 flag on Amlogic g12
- Make amlogic clk drivers configurable in Kconfig
- Fix Renesas VSP clock names to match corrected hardware documentation
- Sigma-delta modulation on Allwinner R40
- Various fixes for at91 clk driver
- Use semicolons instead of commas in some places
- Mark some variables const so they can move to RO memory
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"This contains no changes to the core framework. It is a collection of
various clk driver updates.
The biggest driver updates in terms of lines of code is the Allwinner
driver, closely followed by the Qualcomm and Mediatek drivers. All of
those hit high because we add so many lines of clk data. Coming in
fourth place is i.MX which also adds a bunch of clk data. This
accounts for the new driver additions this time around.
Otherwise the patches are lots of little cleanups and fixes for
various clk drivers that have baked in linux-next for a while. I
suppose one highlight or theme is that more clk drivers are being
updated to work as modules, which is interesting to see such critical
SoC infrastructure work as a loadable module.
New Drivers:
- Support qcom SM8150/SM8250 video and display clks
- Support Mediatek MT8167 clks
- Add clock for CRC block found on vf610 SoCs
- Add support for the Renesas R-Car V3U (R8A779A0) SoC
- Add support for the VSP for Resizing clock on Renesas RZ/G1H
- Support Allwinner A100 SoC clks
Removed Drivers:
- Remove i.MX21 clock driver, as i.MX21 platform support is being
dropped
Updates:
- Change how qcom's display port clks work
- Small non-critical fixes for TI clk driver
- Remove various unused variables in clk drivers
- Allow Rockchip clk driver to be a module
- Remove most __clk_lookup() calls in Samsung drivers (yay!)
- Support building i.MX ARMv8 platforms clock driver as module
- Some kerneldoc fixes here and there
- A couple of minor i.MX clk data corrections
- Update audio clock inverter and fdiv2 flag on Amlogic g12
- Make amlogic clk drivers configurable in Kconfig
- Fix Renesas VSP clock names to match corrected hardware
documentation
- Sigma-delta modulation on Allwinner R40
- Various fixes for at91 clk driver
- Use semicolons instead of commas in some places
- Mark some variables const so they can move to RO memory"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (102 commits)
clk: imx8mq: Fix usdhc parents order
clk: qcom: gdsc: Keep RETAIN_FF bit set if gdsc is already on
clk: Restrict CLK_HSDK to ARC_SOC_HSDK
clk: at91: sam9x60: support only two programmable clocks
clk: ingenic: Respect CLK_SET_RATE_PARENT in .round_rate
clk: ingenic: Don't tag custom clocks with CLK_SET_RATE_PARENT
clk: ingenic: Don't use CLK_SET_RATE_GATE for PLL
clk: ingenic: Use readl_poll_timeout instead of custom loop
clk: ingenic: Use to_clk_info() macro for all clocks
clk: bcm2835: add missing release if devm_clk_hw_register fails
clk: at91: clk-sam9x60-pll: remove unused variable
clk: at91: clk-main: update key before writing AT91_CKGR_MOR
clk: at91: remove the checking of parent_name
clk: clk-prima2: fix return value check in prima2_clk_init()
clk: mmp2: Fix the display clock divider base
clk: pxa: Constify static struct clk_ops
clk: baikal-t1: Mark Ethernet PLL as critical
clk: qoriq: modify MAX_PLL_DIV to 32
clk: axi-clkgen: Set power bits for fractional mode
clk: axi-clkgen: Add support for fractional dividers
...
|
||
|
Peng Fan
|
cbc111d155 |
dt-bindings: reset: imx8mq: add m4 reset
Add the m4 reset used by the remoteproc driver Signed-off-by: Peng Fan <peng.fan@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> |
||
|
Sai Krishna Potthuri
|
a297104ace |
dt-bindings: reset: Updated binding for Versal reset driver
Added documentation and Versal reset indices to describe about Versal reset driver bindings. In Versal all reset indices includes Class, SubClass, Type, Index information whereas class refers to clock, reset, power etc., Underlying firmware in Versal have such classification and expects the ID to be this way. [13:0] - Index bits [19:14] - Type bits [25:20] - SubClass bits [31:26] - Class bits. Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> |
||
|
Thierry Reding
|
639448912b |
arm64: tegra: Initial Tegra234 VDK support
The NVIDIA Tegra234 VDK is a simulation platform for the Orin SoC. It supports a subset of the peripherals that will be available in the final chip and serves as a bootstrapping platform. Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> |
||
|
Yangtao Li
|
fb038ce4db
|
clk: sunxi-ng: add support for the Allwinner A100 CCU
Add support for a100 in the sunxi-ng CCU framework. Signed-off-by: Yangtao Li <frank@allwinnertech.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/1eb41bf6c966a0e54820200650d27a5d4f2ac160.1595572867.git.frank@allwinnertech.com |
||
|
Nicolas Saenz Julienne
|
242841992a |
dt-bindings: reset: Add a binding for the RPi Firmware reset controller
The firmware running on the RPi VideoCore can be used to reset and initialize HW controlled by the firmware. Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Link: https://lore.kernel.org/r/20200629161845.6021-2-nsaenzjulienne@suse.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
||
|
Linus Torvalds
|
05a5b5d8a2 |
Here's some more updates that missed the last pull request because I
happened to tag the tree at an earlier point in the history of clk-next. I must have fat fingered it and checked out an older version of clk-next on this second computer I'm using. This time it actually includes more code for Qualcomm SoCs, the AT91 major updates, and some Rockchip SoC clk driver updates as well. I've corrected this flow so this shouldn't happen again. -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAl80J28RHHNib3lkQGtl cm5lbC5vcmcACgkQrQKIl8bklSVEkRAArVaHkGME9FLC2eOtfh5JSBAITIyvUxXh 6+DVGxt29Rfp24/IL7P05DfDtw402qDnkfeeF7dljgSqS9BimsF5DP2EnLec9j6y EZqZzThMyuS6+UyZ/QSyzpDITqemA9dOccmtve3QPOkgn6BZcfUJGqwIk47Dd/wA udOZCPm+HR4d7H8nzhsfDBIOCPueOV/zDVKPWNSDuuRVLKHOW7OPUvTNo5ZBrOBj 3w6Q3KqHBNVHfrl9b5MdPSEatlTU3hlmm2bskTyVpwMAHKq6H0M0jqCh03jVNRr7 woUtgRzo5KEfM52pZGQTO6U9ifIv4nKv9lIhrZAR4ql3tXGag6hQ3YMahd0sjyUc poJ13JqgLmwTw4B4mbxTS8yW86tlEBXcTc33sT22jt2TrSc5zimoavBzn7NNdzv/ AnPUyAXPJLKFQ2Rx2DNnZ87hSimpPz64MszFcuD2XZpsmohFTretyCUvjaiwQqrL 37Yt/NPo2NVx3yM6BDBs1oXFNMzYrEHpnOEKMfF4JYFHQO8bo5QCwqgiZX8sf1l2 7mQSeae7tDtrWysbJ6L+rSzOcyqCsOoWcM3H2/ydyDgSE4tA+2lU0/AD9jIs8D0U fXHRWJ4eCzGJ8hcdUUhYCMjrsQuerze4neNjYYAZRGbs8PhBKMAVbTl/TAay9rLV QesIjVqhN1o= =/8EM -----END PGP SIGNATURE----- Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull more clk updates from Stephen Boyd: "Here's some more updates that missed the last pull request because I happened to tag the tree at an earlier point in the history of clk-next. I must have fat fingered it and checked out an older version of clk-next on this second computer I'm using. This time it actually includes more code for Qualcomm SoCs, the AT91 major updates, and some Rockchip SoC clk driver updates as well. I've corrected this flow so this shouldn't happen again" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (83 commits) clk: bcm2835: Do not use prediv with bcm2711's PLLs clk: drop unused function __clk_get_flags clk: hsdk: Fix bad dependency on IOMEM dt-bindings: clock: Fix YAML schemas for LPASS clocks on SC7180 clk: mmp: avoid missing prototype warning clk: sparx5: Add Sparx5 SoC DPLL clock driver dt-bindings: clock: sparx5: Add bindings include file clk: qoriq: add LS1021A core pll mux options clk: clk-atlas6: fix return value check in atlas6_clk_init() clk: tegra: pll: Improve PLLM enable-state detection clk: X1000: Add support for calculat REFCLK of USB PHY. clk: JZ4780: Reformat the code to align it. clk: JZ4780: Add functions for enable and disable USB PHY. clk: Ingenic: Add RTC related clocks for Ingenic SoCs. dt-bindings: clock: Add tabs to align code. dt-bindings: clock: Add RTC related clocks for Ingenic SoCs. clk: davinci: Use fallthrough pseudo-keyword clk: imx: Use fallthrough pseudo-keyword clk: qcom: gcc-sdm660: Fix up gcc_mss_mnoc_bimc_axi_clk clk: qcom: gcc-sdm660: Add missing modem reset ... |
||
|
Cristian Ciocaltea
|
fac1d443a2 |
dt-bindings: reset: Add binding constants for Actions S500 RMU
Add device tree binding constants for Actions Semi S500 SoC Reset Management Unit (RMU). Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/daf615160b3be9f38dcf7926cc82128c9c2d73e3.1593788312.git.cristian.ciocaltea@gmail.com Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> |
||
|
Alexander A. Klimov
|
ffebbecaaa |
reset: Replace HTTP links with HTTPS ones
Rationale:
Reduces attack surface on kernel devs opening the links for MITM
as HTTPS traffic is much harder to manipulate.
Deterministic algorithm:
For each file:
If not .svg:
For each line:
If doesn't contain `\bxmlns\b`:
For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`:
If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`:
If both the HTTP and HTTPS versions
return 200 OK and serve the same content:
Replace HTTP with HTTPS.
Signed-off-by: Alexander A. Klimov <grandmaster@al2klimov.de>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
|
||
|
Linus Torvalds
|
6f630784cc |
This time around we have 4 lines of diff in the core framework, removing a
function that isn't used anymore. Otherwise the main new thing for the common
clk framework is that it is selectable in the Kconfig language now. Hopefully
this will let clk drivers and clk consumers be testable on more than the
architectures that support the clk framework. The goal is to introduce some
Kunit tests for the framework.
Outside of the core framework we have the usual set of various driver updates
and non-critical fixes. The dirstat shows that the new Baikal-T1 driver is the
largest addition this time around in terms of lines of code. After that the x86
(Intel), Qualcomm, and Mediatek drivers introduce many lines to support new or
upcoming SoCs. After that the dirstat shows the usual suspects working on their
SoC support by fixing minor bugs, correcting data and converting some of their
DT bindings to YAML.
Core:
- Allow the COMMON_CLK config to be selectable
New Drivers:
- Clk driver for Baikal-T1 SoCs
- Mediatek MT6765 clock support
- Support for Intel Agilex clks
- Add support for X1830 and X1000 Ingenic SoC clk controllers
- Add support for the new Renesas RZ/G1H (R8A7742) SoC
- Add support for Qualcomm's MSM8939 Generic Clock Controller
Updates:
- Support IDT VersaClock 5P49V5925
- Bunch of updates for HSDK clock generation unit (CGU) driver
- Start making audio and GPU clks work on Marvell MMP2/MMP3 SoCs
- Add some GPU, NPU, and UFS clks to Qualcomm SM8150 driver
- Enable supply regulators for GPU gdscs on Qualcomm SoCs
- Add support for Si5342, Si5344 and Si5345 chips
- Support custom flags in Xilinx zynq firmware
- Various small fixes to the Xilinx clk driver
- A single minor rounding fix for the legacy Allwinner clock support
- A few patches from Abel Vesa as preparation of adding audiomix clock support
on i.MX
- A couple of cleanups from Anson Huang for i.MX clk-sscg-pll and clk-pllv3
drivers
- Drop dependency on ARM64 for i.MX8M clock driver, to support aarch32 mode on
aarch64 hardware
- A series from Peng Fan to improve i.MX8M clock drivers, using composite
clock for core and bus clk slice
- Set a better parent clock for flexcan on i.MX6UL to support CiA102 defined
bit rates
- A couple changes for EMC frequency scaling on Tegra210
- Support for CPU frequency scaling on Tegra20/Tegra30
- New clk gate for CSI test pattern generator on Tegra210
- Regression fixes for Samsung exynos542x and exynos5433 SoCs
- Use of fallthrough; attribute for Samsung s3c24xx
- Updates and fixup HDMI and video clocks on Meson8b
- Fixup reset polarity on Meson8b
- Fix GPU glitch free mux switch on Meson gx and g12
- A minor fix for the currently unused suspend/resume handling on Renesas RZ/A1 and RZ/A2
- Two more conversions of Renesas DT bindings to json-schema
- Add support for the USB 2.0 clock selector on Renesas R-Car M3-W+
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"This time around we have four lines of diff in the core framework,
removing a function that isn't used anymore. Otherwise the main new
thing for the common clk framework is that it is selectable in the
Kconfig language now. Hopefully this will let clk drivers and clk
consumers be testable on more than the architectures that support the
clk framework. The goal is to introduce some Kunit tests for the
framework.
Outside of the core framework we have the usual set of various driver
updates and non-critical fixes. The dirstat shows that the new
Baikal-T1 driver is the largest addition this time around in terms of
lines of code. After that the x86 (Intel), Qualcomm, and Mediatek
drivers introduce many lines to support new or upcoming SoCs. After
that the dirstat shows the usual suspects working on their SoC support
by fixing minor bugs, correcting data and converting some of their DT
bindings to YAML.
Core:
- Allow the COMMON_CLK config to be selectable
New Drivers:
- Clk driver for Baikal-T1 SoCs
- Mediatek MT6765 clock support
- Support for Intel Agilex clks
- Add support for X1830 and X1000 Ingenic SoC clk controllers
- Add support for the new Renesas RZ/G1H (R8A7742) SoC
- Add support for Qualcomm's MSM8939 Generic Clock Controller
Updates:
- Support IDT VersaClock 5P49V5925
- Bunch of updates for HSDK clock generation unit (CGU) driver
- Start making audio and GPU clks work on Marvell MMP2/MMP3 SoCs
- Add some GPU, NPU, and UFS clks to Qualcomm SM8150 driver
- Enable supply regulators for GPU gdscs on Qualcomm SoCs
- Add support for Si5342, Si5344 and Si5345 chips
- Support custom flags in Xilinx zynq firmware
- Various small fixes to the Xilinx clk driver
- A single minor rounding fix for the legacy Allwinner clock support
- A few patches from Abel Vesa as preparation of adding audiomix
clock support on i.MX
- A couple of cleanups from Anson Huang for i.MX clk-sscg-pll and
clk-pllv3 drivers
- Drop dependency on ARM64 for i.MX8M clock driver, to support
aarch32 mode on aarch64 hardware
- A series from Peng Fan to improve i.MX8M clock drivers, using
composite clock for core and bus clk slice
- Set a better parent clock for flexcan on i.MX6UL to support CiA102
defined bit rates
- A couple changes for EMC frequency scaling on Tegra210
- Support for CPU frequency scaling on Tegra20/Tegra30
- New clk gate for CSI test pattern generator on Tegra210
- Regression fixes for Samsung exynos542x and exynos5433 SoCs
- Use of fallthrough; attribute for Samsung s3c24xx
- Updates and fixup HDMI and video clocks on Meson8b
- Fixup reset polarity on Meson8b
- Fix GPU glitch free mux switch on Meson gx and g12
- A minor fix for the currently unused suspend/resume handling on
Renesas RZ/A1 and RZ/A2
- Two more conversions of Renesas DT bindings to json-schema
- Add support for the USB 2.0 clock selector on Renesas R-Car M3-W+"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (155 commits)
clk: mediatek: Remove ifr{0,1}_cfg_regs structures
clk: baikal-t1: remove redundant assignment to variable 'divider'
clk: baikal-t1: fix spelling mistake "Uncompatible" -> "Incompatible"
dt-bindings: clock: Add a missing include to MMP Audio Clock binding
dt: Add bindings for IDT VersaClock 5P49V5925
clk: vc5: Add support for IDT VersaClock 5P49V6965
clk: Add Baikal-T1 CCU Dividers driver
clk: Add Baikal-T1 CCU PLLs driver
dt-bindings: clk: Add Baikal-T1 CCU Dividers binding
dt-bindings: clk: Add Baikal-T1 CCU PLLs binding
clk: mediatek: assign the initial value to clk_init_data of mtk_mux
clk: mediatek: Add MT6765 clock support
clk: mediatek: add mt6765 clock IDs
dt-bindings: clock: mediatek: document clk bindings vcodecsys for Mediatek MT6765 SoC
dt-bindings: clock: mediatek: document clk bindings mipi0a for Mediatek MT6765 SoC
dt-bindings: clock: mediatek: document clk bindings for Mediatek MT6765 SoC
CLK: HSDK: CGU: add support for 148.5MHz clock
CLK: HSDK: CGU: support PLL bypassing
CLK: HSDK: CGU: check if PLL is bypassed first
clk: clk-si5341: Add support for the Si5345 series
...
|
||
|
Linus Torvalds
|
9d71d3cd9e |
ARM: DT changes for v5.8
This is the set of device tree changes, mostly covering new
hardware support, with 577 patches touching a little over 500
files.
There are five new Arm SoCs supported in this release, all of
them for existing SoC families:
- Realtek RTD1195, RTD1395 and RTD1619 -- three SoCs used in
both NAS devices and Android Set-top-box designs, along
with the "Horseradish", "Lion Skin" and "Mjolnir" reference
platforms; the Mele X1000 and Xnano X5 set-top-boxes and
the Banana Pi BPi-M4 single-board computer.
- Renesas RZ/G1H (r8a7742) -- a high-end 32-bit industrial SoC
and the iW-RainboW-G21D-Qseven-RZG1H board/SoM
- Rockchips RK3326 -- low-end 64-bit SoC along with the
Odroid-GO Advance game console
Newly added machines on already supported SoCs are:
- AMLogic S905D based Smartlabs SML-5442TW TV box
- AMLogic S905X3 based ODROID-C4 SBC
- AMLogic S922XH based Beelink GT-King Pro TV box
- Allwinner A20 based Olimex A20-OLinuXino-LIME-eMMC SBC
- Aspeed ast2500 based BMCs in Facebook x86 "Yosemite V2"
and YADRO OpenPower P9 "Nicole"
- Marvell Kirkwood based Check Point L-50 router
- Mediatek MT8173 based Elm/Hana Chromebook laptops
- Microchip SAMA5D2 "Industrial Connectivity Platform"
reference board
- NXP i.MX8m based Beacon i.MX8m-Mini SoM development kit
- Octavo OSDMP15x based Linux Automation MC-1 development board
- Qualcomm SDM630 based Xiaomi Redmi Note 7 phone
- Realtek RTD1295 based Xnano X5 TV Box
- STMicroelectronics STM32MP1 based Stinger96 single-board
computer and IoT Box
- Samsung Exynos4210 based based Samsung Galaxy S2 phone
- Socionext Uniphier based Akebi96 SBC
- TI Keystone based K2G Evaluation board
- TI am5729 based Beaglebone-AI development board
Include device descriptions for additional hardware support in existing
SoCs and machines based on all major SoC platforms:
- AMlogic Meson
- Allwinner sunxi
- Arm Juno/VFP/Vexpress/Integrator
- Broadcom bcm283x/bcm2711
- Hisilicon hi6220
- Marvell EBU
- Mediatek MT27xx, MT76xx, MT81xx and MT67xx
- Microchip SAMA5D2
- NXP i.MX6/i.MX7/i.MX8 and Layerscape
- Nvidia Tegra
- Qualcomm Snapdragon
- Renesas r8a77961, r8a7791
- Rockchips RK32xx/RK33xx
- ST-Ericsson ux500
- STMicroelectronics SMT32
- Samsung Exynos and S5PV210
- Socionext Uniphier
- TI OMAP5/DRA7 and Keystone
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Merge tag 'arm-dt-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM devicetree updates from Arnd Bergmann:
"This is the set of device tree changes, mostly covering new hardware
support, with 577 patches touching a little over 500 files.
There are five new Arm SoCs supported in this release, all of them for
existing SoC families:
- Realtek RTD1195, RTD1395 and RTD1619 -- three SoCs used in both NAS
devices and Android Set-top-box designs, along with the
"Horseradish", "Lion Skin" and "Mjolnir" reference platforms; the
Mele X1000 and Xnano X5 set-top-boxes and the Banana Pi BPi-M4
single-board computer.
- Renesas RZ/G1H (r8a7742) -- a high-end 32-bit industrial SoC and
the iW-RainboW-G21D-Qseven-RZG1H board/SoM
- Rockchips RK3326 -- low-end 64-bit SoC along with the Odroid-GO
Advance game console
Newly added machines on already supported SoCs are:
- AMLogic S905D based Smartlabs SML-5442TW TV box
- AMLogic S905X3 based ODROID-C4 SBC
- AMLogic S922XH based Beelink GT-King Pro TV box
- Allwinner A20 based Olimex A20-OLinuXino-LIME-eMMC SBC
- Aspeed ast2500 based BMCs in Facebook x86 "Yosemite V2" and YADRO
OpenPower P9 "Nicole"
- Marvell Kirkwood based Check Point L-50 router
- Mediatek MT8173 based Elm/Hana Chromebook laptops
- Microchip SAMA5D2 "Industrial Connectivity Platform" reference
board
- NXP i.MX8m based Beacon i.MX8m-Mini SoM development kit
- Octavo OSDMP15x based Linux Automation MC-1 development board
- Qualcomm SDM630 based Xiaomi Redmi Note 7 phone
- Realtek RTD1295 based Xnano X5 TV Box
- STMicroelectronics STM32MP1 based Stinger96 single-board computer
and IoT Box
- Samsung Exynos4210 based based Samsung Galaxy S2 phone
- Socionext Uniphier based Akebi96 SBC
- TI Keystone based K2G Evaluation board
- TI am5729 based Beaglebone-AI development board
Include device descriptions for additional hardware support in
existing SoCs and machines based on all major SoC platforms:
- AMlogic Meson
- Allwinner sunxi
- Arm Juno/VFP/Vexpress/Integrator
- Broadcom bcm283x/bcm2711
- Hisilicon hi6220
- Marvell EBU
- Mediatek MT27xx, MT76xx, MT81xx and MT67xx
- Microchip SAMA5D2
- NXP i.MX6/i.MX7/i.MX8 and Layerscape
- Nvidia Tegra
- Qualcomm Snapdragon
- Renesas r8a77961, r8a7791
- Rockchips RK32xx/RK33xx
- ST-Ericsson ux500
- STMicroelectronics SMT32
- Samsung Exynos and S5PV210
- Socionext Uniphier
- TI OMAP5/DRA7 and Keystone"
* tag 'arm-dt-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (564 commits)
ARM: dts: keystone: Rename "msmram" node to "sram"
arm: dts: mt2712: add uart APDMA to device tree
arm64: dts: mt8183: add mmc node
arm64: dts: mt2712: add ethernet device node
arm64: tegra: Make the RTC a wakeup source on Jetson Nano and TX1
ARM: dts: mmp3: Add the fifth SD HCI
ARM: dts: berlin*: Fix up the SDHCI node names
ARM: dts: mmp3: Fix USB & USB PHY node names
ARM: dts: mmp3: Fix L2 cache controller node name
ARM: dts: mmp*: Fix up encoding of the /rtc interrupts property
ARM: dts: pxa*: Fix up encoding of the /rtc interrupts property
ARM: dts: pxa910: Fix the gpio interrupt cell number
ARM: dts: pxa3xx: Fix up encoding of the /gpio interrupts property
ARM: dts: pxa168: Fix the gpio interrupt cell number
ARM: dts: pxa168: Add missing address/size cells to i2c nodes
ARM: dts: dove: Fix interrupt controller node name
ARM: dts: kirkwood: Fix interrupt controller node name
arm64: dts: Add SC9863A emmc and sd card nodes
arm64: dts: Add SC9863A clock nodes
arm64: dts: mt6358: add PMIC MT6358 related nodes
...
|
||
|
Stephen Boyd
|
166e4b4841 |
Merge branches 'clk-vc5', 'clk-hsdk', 'clk-mediatek' and 'clk-baikal' into clk-next
- Support IDT VersaClock 5P49V5925 - Bunch of updates for HSDK clock generation unit (CGU) driver - New clk driver for Baikal-T1 SoCs * clk-vc5: dt: Add bindings for IDT VersaClock 5P49V5925 clk: vc5: Add support for IDT VersaClock 5P49V6965 * clk-hsdk: CLK: HSDK: CGU: add support for 148.5MHz clock CLK: HSDK: CGU: support PLL bypassing CLK: HSDK: CGU: check if PLL is bypassed first * clk-mediatek: clk: mediatek: assign the initial value to clk_init_data of mtk_mux clk: mediatek: Add MT6765 clock support clk: mediatek: add mt6765 clock IDs dt-bindings: clock: mediatek: document clk bindings vcodecsys for Mediatek MT6765 SoC dt-bindings: clock: mediatek: document clk bindings mipi0a for Mediatek MT6765 SoC dt-bindings: clock: mediatek: document clk bindings for Mediatek MT6765 SoC * clk-baikal: clk: Add Baikal-T1 CCU Dividers driver clk: Add Baikal-T1 CCU PLLs driver dt-bindings: clk: Add Baikal-T1 CCU Dividers binding dt-bindings: clk: Add Baikal-T1 CCU PLLs binding |
||
|
Serge Semin
|
11ea09b9e2 |
dt-bindings: clk: Add Baikal-T1 CCU Dividers binding
After being gained by the CCU PLLs the signals must be transformed to be suitable for the clock-consumers. This is done by a set of dividers embedded into the CCU. A first block of dividers is used to create reference clocks for AXI-bus of high-speed peripheral IP-cores of the chip. The second block dividers alter the PLLs output signals to be then consumed by SoC peripheral devices. Both block DT nodes are ordinary clock-providers with standard set of properties supported. But in addition to that each clock provider can be used to reset the corresponding clock domain. This makes the AXI-bus and System Devices CCU DT nodes to be also reset-providers. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru> Cc: Arnd Bergmann <arnd@arndb.de> Cc: linux-mips@vger.kernel.org Link: https://lore.kernel.org/r/20200526222056.18072-3-Sergey.Semin@baikalelectronics.ru Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> |
||
|
Arnd Bergmann
|
34a07a8da3 |
arm64: dts: Amlogic updates for v5.8
Highlights: - new boards :Beelink GT-King Pro (G12B SoC), Smartlabs SML-5442TW (S905D), Hardkernel ODROID-C4 (SM1) - audio: support for GX-family SoCs - audio: internal DAC support - use the new USB control driver for GXL and GXM -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEe4dGDhaSf6n1v/EMWTcYmtP7xmUFAl7G0fMACgkQWTcYmtP7 xmXYOg/8Dp9b4OpTxZ8GQmD6sUrPFxnWi9mckDGYAqvtzNA2MdTzrkJAo6D9jQqC 83uqqVGUKmgSuDnUKfesLLUHPu464Ab2cWLsuKsMIJNO+B9sYX0SAzePT53mdKDR WDCS9h0UN+smL3WjEb/dZ3gthiXYaBhSEtMyTLq47MJTcbCwvVsvOJmdM2pXkzRx 3kosB22+vLVWyih2tSSIdfzqn3nNFRh1Cs0pnqynMjfkTIsr5XTgmN+BFKmFVefA qHPpgJ1fGwRBS6sQg/1h3H1zC6pUAXCYXOhaBeOzOumVp3jxR3E0aqux8/CwqEWX ppkU6sCpuI/BZcHK+76+87SUyBOuuZ9TK2SQuoNGEzT0sZ8GZHTfRD/Edw5YYtGe l9RpJyq11QOPEv+/q5nNMD9mLzd2pH5WItiO6inj0V03g2jS5t2Kz05awolDbESZ ELPq5iKHttdxvcV1e5HK5HwKevkXW2+EJSaBRTzFneheQllryZubPVCfV02Ybijf k97WLs2swKpRjvsIdg2o6MXy8xd/kmj5zclgj6z2S9FF+rgTl9jw3l/GIDZ2kgEx 0YXQL9Pec8xtdux//WwIP931TIHUnI5IUTjGOWy1Ch/QLwA/BxVy+BeQVCAidN3Y 5U6NbowE5UdozThi1BMxVokPWoF9XJlpcQISrmuVrgRtnbfiaMY= =JbXj -----END PGP SIGNATURE----- Merge tag 'amlogic-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/dt arm64: dts: Amlogic updates for v5.8 Highlights: - new boards :Beelink GT-King Pro (G12B SoC), Smartlabs SML-5442TW (S905D), Hardkernel ODROID-C4 (SM1) - audio: support for GX-family SoCs - audio: internal DAC support - use the new USB control driver for GXL and GXM * tag 'amlogic-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: (33 commits) arm64: dts: meson-g12b-gtking-pro: add initial device-tree dt-bindings: arm: amlogic: add support for the Beelink GT-King Pro arm64: dts: meson-g12b-gtking: add initial device-tree dt-bindings: arm: amlogic: add support for the Beelink GT-King arm64: dts: meson: convert ugoos-am6 to common w400 dtsi arm64: dts: meson: add ethernet interrupt to wetek dtsi arm64: dts: meson: add support for the Smartlabs SML-5442TW dt-bindings: arm: amlogic: add support for the Smartlabs SML-5442TW dt-bindings: add vendor prefix for Smartlabs LLC arm64: dts: meson: g12: add internal DAC glue arm64: dts: meson: g12: add internal DAC arm64: dts: meson: libretech-pc: add internal DAC support arm64: dts: meson: libretech-ac: add internal DAC support arm64: dts: meson: libretech-cc: add internal DAC support arm64: dts: meson: p230-q200: add internal DAC support arm64: dts: meson: gxl: add acodec support arm64: dts: meson-sm1: add support for Hardkernel ODROID-C4 dt-bindings: arm: amlogic: add odroid-c4 bindings arm64: dts: meson-sm1: add cpu thermal nodes arm64: dts: meson-g12b: move G12B thermal nodes to meson-g12b.dtsi ... Link: https://lore.kernel.org/r/5ec6f56a.1c69fb81.fc5d5.9ca6@mx.google.com Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
||
|
Bryan O'Donoghue
|
4c71d6abc4 |
clk: qcom: Add DT bindings for MSM8939 GCC
Add compatible strings and the include files for the MSM8939 GCC. Cc: Andy Gross <agross@kernel.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: linux-arm-msm@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Tested-by: Vincent Knecht <vincent.knecht@mailoo.org> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lkml.kernel.org/r/20200512115023.2856617-2-bryan.odonoghue@linaro.org Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> |
||
|
Jerome Brunet
|
3a5fc2520b |
dt-bindings: reset: meson: add gxl internal dac reset
Add the reset line of the internal DAC found on the amlogic gxl SoC family Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> |
||
|
Anson Huang
|
c4e181d6fe |
dt-bindings: reset: imx7: Document usage on i.MX8MP SoC
The driver now supports i.MX8MP, so update bindings accordingly. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> |
||
|
Anson Huang
|
ecd910f442 |
dt-bindings: reset: imx7: Add support for i.MX8MN
i.MX8MN can reuse i.MX8MQ's reset driver, update the compatible property and related info to support i.MX8MN. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> |
||
|
Andreas Färber
|
378788120b |
dt-bindings: reset: rtd1295: Add SB2 reset
Add a constant for reset3 SB2, based on downstream crt_sys_reg.h. Acked-by: Rob Herring <robh@kernel.org> Acked-by: James Tai <james.tai@realtek.com> Signed-off-by: Andreas Färber <afaerber@suse.de> |
||
|
Andreas Färber
|
63313c1ceb |
dt-bindings: reset: Add Realtek RTD1195
Add a header with symbolic reset indices for Realtek RTD1195 SoC. Naming was derived from BSP register description headers. Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: James Tai <james.tai@realtek.com> Signed-off-by: Andreas Färber <afaerber@suse.de> |
||
|
Linus Torvalds
|
eab3540562 |
ARM: SoC-related driver updates
Various driver updates for platforms:
- Nvidia: Fuse support for Tegra194, continued memory controller pieces
for Tegra30
- NXP/FSL: Refactorings of QuickEngine drivers to support ARM/ARM64/PPC
- NXP/FSL: i.MX8MP SoC driver pieces
- TI Keystone: ring accelerator driver
- Qualcomm: SCM driver cleanup/refactoring + support for new SoCs.
- Xilinx ZynqMP: feature checking interface for firmware. Mailbox
communication for power management
- Overall support patch set for cpuidle on more complex hierarchies
(PSCI-based)
+ Misc cleanups, refactorings of Marvell, TI, other platforms.
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Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC-related driver updates from Olof Johansson:
"Various driver updates for platforms:
- Nvidia: Fuse support for Tegra194, continued memory controller
pieces for Tegra30
- NXP/FSL: Refactorings of QuickEngine drivers to support
ARM/ARM64/PPC
- NXP/FSL: i.MX8MP SoC driver pieces
- TI Keystone: ring accelerator driver
- Qualcomm: SCM driver cleanup/refactoring + support for new SoCs.
- Xilinx ZynqMP: feature checking interface for firmware. Mailbox
communication for power management
- Overall support patch set for cpuidle on more complex hierarchies
(PSCI-based)
and misc cleanups, refactorings of Marvell, TI, other platforms"
* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (166 commits)
drivers: soc: xilinx: Use mailbox IPI callback
dt-bindings: power: reset: xilinx: Add bindings for ipi mailbox
drivers: soc: ti: knav_qmss_queue: Pass lockdep expression to RCU lists
MAINTAINERS: Add brcmstb PCIe controller entry
soc/tegra: fuse: Unmap registers once they are not needed anymore
soc/tegra: fuse: Correct straps' address for older Tegra124 device trees
soc/tegra: fuse: Warn if straps are not ready
soc/tegra: fuse: Cache values of straps and Chip ID registers
memory: tegra30-emc: Correct error message for timed out auto calibration
memory: tegra30-emc: Firm up hardware programming sequence
memory: tegra30-emc: Firm up suspend/resume sequence
soc/tegra: regulators: Do nothing if voltage is unchanged
memory: tegra: Correct reset value of xusb_hostr
soc/tegra: fuse: Add APB DMA dependency for Tegra20
bus: tegra-aconnect: Remove PM_CLK dependency
dt-bindings: mediatek: add MT6765 power dt-bindings
soc: mediatek: cmdq: delete not used define
memory: tegra: Add support for the Tegra194 memory controller
memory: tegra: Only include support for enabled SoCs
memory: tegra: Support DVFS on Tegra186 and later
...
|
||
|
Linus Torvalds
|
f4a6365ae8 |
There are a few changes to the core framework this time around, in addition to
the normal collection of driver updates to support new SoCs, fix incorrect
data, and convert various drivers to clk_hw based APIs.
In the core, we allow clk_ops::init() to return an error code now so that we
can fail clk registration if the callback does something like fail to allocate
memory. We also add a new "terminate" clk_op so that things done in
clk_ops::init() can be undone, e.g. free memory. We also spit out a warning now
when critical clks fail to enable and we support changing clk rates and
enable/disable state through debugfs when developers compile the kernel
themselves.
On the driver front, we get support for what seems like a lot of Qualcomm and
NXP SoCs given that those vendors dominate the diffstat. There are a couple new
drivers for Xilinx and Amlogic SoCs too. The updates are all small things like
fixing the way glitch free muxes switch parents, avoiding div-by-zero problems,
or fixing data like parent names. See the updates section below for more
details.
Finally, the "basic" clk types have been converted to support specifying
parents with clk_hw pointers. This work includes an overhaul of the fixed-rate
clk type to be more modern by using clk_hw APIs.
Core:
- Let clk_ops::init() return an error code
- Add a clk_ops::terminate() callback to undo clk_ops::init()
- Warn about critical clks that fail to enable or prepare
- Support dangerous debugfs actions on clks with dead code
New Drivers:
- Support for Xilinx Versal platform clks
- Display clk controller on qcom sc7180
- Video clk controller on qcom sc7180
- Graphics clk controller on qcom sc7180
- CPU PLLs for qcom msm8916
- Move qcom msm8974 gfx3d clk to RPM control
- Display port clk support on qcom sdm845 SoCs
- Global clk controller on qcom ipq6018
- Add a driver for BCLK of Freescale SAI cores
- Add cam, vpe and sgx clock support for TI dra7
- Add aess clock support for TI omap5
- Enable clks for CPUfreq on Allwinner A64 SoCs
- Add Amlogic meson8b DDR clock controller
- Add input clocks to Amlogic meson8b controllers
- Add SPIBSC (SPI FLASH) clock on Renesas RZ/A2
- i.MX8MP clk driver support
Updates:
- Convert gpio, fixed-factor, mux, gate, divider basic clks to hw based APIs
- Detect more PRMCU variants in ux500 driver
- Adjust the composite clk type to new way of describing clk parents
- Fixes for clk controllers on qcom msm8998 SoCs
- Fix gmac main clock for TI dra7
- Move TI dra7-atl clock header to correct location
- Fix hidden node name dependency on TI clkctrl clocks
- Fix Amlogic meson8b mali clock update using the glitch free mux
- Fix Amlogic pll driver division by zero at init
- Prepare for split of Renesas R-Car H3 ES1.x and ES2.0+ config symbols
- Switch more i.MX clk drivers to clk_hw based APIs
- Disable non-functional divider between pll4_audio_div and
pll4_post_div on imx6q
- Fix watchdog2 clock name typo in imx7ulp clock driver
- Set CLK_GET_RATE_NOCACHE flag for DRAM related clocks on i.MX8M SoCs
- Suppress bind attrs for i.MX8M clock driver
- Add a big comment in imx8qxp-lpcg driver to tell why
devm_platform_ioremap_resource() shouldn't be used for the driver
- A correction on i.MX8MN usb1_ctrl parent clock setting
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"There are a few changes to the core framework this time around, in
addition to the normal collection of driver updates to support new
SoCs, fix incorrect data, and convert various drivers to clk_hw based
APIs.
In the core, we allow clk_ops::init() to return an error code now so
that we can fail clk registration if the callback does something like
fail to allocate memory. We also add a new "terminate" clk_op so that
things done in clk_ops::init() can be undone, e.g. free memory. We
also spit out a warning now when critical clks fail to enable and we
support changing clk rates and enable/disable state through debugfs
when developers compile the kernel themselves.
On the driver front, we get support for what seems like a lot of
Qualcomm and NXP SoCs given that those vendors dominate the diffstat.
There are a couple new drivers for Xilinx and Amlogic SoCs too. The
updates are all small things like fixing the way glitch free muxes
switch parents, avoiding div-by-zero problems, or fixing data like
parent names. See the updates section below for more details.
Finally, the "basic" clk types have been converted to support
specifying parents with clk_hw pointers. This work includes an
overhaul of the fixed-rate clk type to be more modern by using clk_hw
APIs.
Core:
- Let clk_ops::init() return an error code
- Add a clk_ops::terminate() callback to undo clk_ops::init()
- Warn about critical clks that fail to enable or prepare
- Support dangerous debugfs actions on clks with dead code
New Drivers:
- Support for Xilinx Versal platform clks
- Display clk controller on qcom sc7180
- Video clk controller on qcom sc7180
- Graphics clk controller on qcom sc7180
- CPU PLLs for qcom msm8916
- Move qcom msm8974 gfx3d clk to RPM control
- Display port clk support on qcom sdm845 SoCs
- Global clk controller on qcom ipq6018
- Add a driver for BCLK of Freescale SAI cores
- Add cam, vpe and sgx clock support for TI dra7
- Add aess clock support for TI omap5
- Enable clks for CPUfreq on Allwinner A64 SoCs
- Add Amlogic meson8b DDR clock controller
- Add input clocks to Amlogic meson8b controllers
- Add SPIBSC (SPI FLASH) clock on Renesas RZ/A2
- i.MX8MP clk driver support
Updates:
- Convert gpio, fixed-factor, mux, gate, divider basic clks to hw
based APIs
- Detect more PRMCU variants in ux500 driver
- Adjust the composite clk type to new way of describing clk parents
- Fixes for clk controllers on qcom msm8998 SoCs
- Fix gmac main clock for TI dra7
- Move TI dra7-atl clock header to correct location
- Fix hidden node name dependency on TI clkctrl clocks
- Fix Amlogic meson8b mali clock update using the glitch free mux
- Fix Amlogic pll driver division by zero at init
- Prepare for split of Renesas R-Car H3 ES1.x and ES2.0+ config
symbols
- Switch more i.MX clk drivers to clk_hw based APIs
- Disable non-functional divider between pll4_audio_div and
pll4_post_div on imx6q
- Fix watchdog2 clock name typo in imx7ulp clock driver
- Set CLK_GET_RATE_NOCACHE flag for DRAM related clocks on i.MX8M
SoCs
- Suppress bind attrs for i.MX8M clock driver
- Add a big comment in imx8qxp-lpcg driver to tell why
devm_platform_ioremap_resource() shouldn't be used for the driver
- A correction on i.MX8MN usb1_ctrl parent clock setting"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (140 commits)
dt/bindings: clk: fsl,plldig: Drop 'bindings' from schema id
clk: ls1028a: Fix warning on clamp() usage
clk: qoriq: add ls1088a hwaccel clocks support
clk: ls1028a: Add clock driver for Display output interface
dt/bindings: clk: Add YAML schemas for LS1028A Display Clock bindings
clk: fsl-sai: new driver
dt-bindings: clock: document the fsl-sai driver
clk: composite: add _register_composite_pdata() variants
clk: qcom: rpmh: Sort OF match table
dt-bindings: fix warnings in validation of qcom,gcc.yaml
dt-binding: fix compilation error of the example in qcom,gcc.yaml
clk: zynqmp: Add support for clock with CLK_DIVIDER_POWER_OF_TWO flag
clk: zynqmp: Fix divider calculation
clk: zynqmp: Add support for get max divider
clk: zynqmp: Warn user if clock user are more than allowed
clk: zynqmp: Extend driver for versal
dt-bindings: clock: Add bindings for versal clock driver
clk: ti: clkctrl: Fix hidden dependency to node name
clk: ti: add clkctrl data dra7 sgx
clk: ti: omap5: Add missing AESS clock
...
|
||
|
Sricharan R
|
d15b1ff1bd |
clk: qcom: Add DT bindings for ipq6018 gcc clock controller
Add the compatible strings and the include file for ipq6018 gcc clock controller. Co-developed-by: Anusha Canchi Ramachandra Rao <anusharao@codeaurora.org> Signed-off-by: Anusha Canchi Ramachandra Rao <anusharao@codeaurora.org> Co-developed-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Co-developed-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Link: https://lkml.kernel.org/r/1578557121-423-2-git-send-email-sricharan@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org> |
||
|
Tomer Maimon
|
a5df0d4e9d |
dt-bindings: reset: Add binding constants for NPCM7xx reset controller
Add device tree binding constants for Nuvoton BMC NPCM7xx reset controller. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> |
||
|
Martin Blumenstingl
|
4881873f4c |
dt-bindings: reset: meson8b: fix duplicate reset IDs
According to the public S805 datasheet the RESET2 register uses the
following bits for the PIC_DC, PSC and NAND reset lines:
- PIC_DC is at bit 3 (meaning: RESET_VD_RMEM + 3)
- PSC is at bit 4 (meaning: RESET_VD_RMEM + 4)
- NAND is at bit 5 (meaning: RESET_VD_RMEM + 4)
Update the reset IDs of these three reset lines so they don't conflict
with PIC_DC and map to the actual hardware reset lines.
Fixes:
|
||
|
Linus Torvalds
|
eb275167d1 |
ARM: Device-tree updates
As always, the bulk of updates. Some of the news this cycle:
New SoC descriptions:
- Broadcom BCM2711
- Amlogic Meson A1 and G12
- Freescale S32V234
- Marvell Armada AP807/AP807-quad and CP115
- Realtek RTD1293 and RTD1296
- Rockchip RK3308
New boards and platforms:
- Allwinner: NanoPi Duo2
- Amlogic: Ugoos am6
- Atmel at91: Overkiz Kizbox2/4
- Broadcom: RPi4, Luxul XWC-2000
- Marvell: New Espressobin flavor
- NXP: i.MX8MN LPDDR4 EVK, i.MX8QXP Colibri, S32V234 EVB, Netronix
E60K02 and Kobo Clara HD, Kontron N6311 and N6411, OPOS6UL and
OPOS6ULDev
- Renesas: Salvator-XS
- Rockchip: Beelink A1 (rk3308), rk3308 eval boards, rk3399-roc-pc
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM Device-tree updates from Olof Johansson:
"As always, the bulk of updates. Some of the news this cycle:
New SoC descriptions:
- Broadcom BCM2711
- Amlogic Meson A1 and G12
- Freescale S32V234
- Marvell Armada AP807/AP807-quad and CP115
- Realtek RTD1293 and RTD1296
- Rockchip RK3308
New boards and platforms:
- Allwinner: NanoPi Duo2
- Amlogic: Ugoos am6
- Atmel at91: Overkiz Kizbox2/4
- Broadcom: RPi4, Luxul XWC-2000
- Marvell: New Espressobin flavor
- NXP: i.MX8MN LPDDR4 EVK, i.MX8QXP Colibri, S32V234 EVB, Netronix
E60K02 and Kobo Clara HD, Kontron N6311 and N6411, OPOS6UL and
OPOS6ULDev
- Renesas: Salvator-XS
- Rockchip: Beelink A1 (rk3308), rk3308 eval boards, rk3399-roc-pc"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (653 commits)
ARM: dts: logicpd-torpedo: Disable USB Host
arm: dts: mt6323: add keys, power-controller, rtc and codec
arm64: dts: mt8183: add systimer0 device node
dt-bindings: mediatek: update bindings for MT8183 systimer
arm64: dts: rockchip: fix sdmmc detection on boot on rk3328-roc-cc
arm64: dts: rockchip: Split rk3399-roc-pc for with and without mezzanine board.
arm64: dts: rockchip: Add Beelink A1
dt-bindings: ARM: rockchip: Add Beelink A1
arm64: dts: rockchip: Add RK3328 audio pipelines
arm64: dts: ti: k3-j721e-common-proc-board: Add USB ports
arm64: dts: ti: k3-j721e-main: add USB controller nodes
ARM: dts: aspeed-g6: Add timer description
ARM: dts: aspeed: ast2600evb: Enable i2c buses
ARM: dts: at91: add a dts and dtsi file for kizbox2 based boards
dt-bindings: arm: at91: Document Kizbox2-2 board binding
arm64: dts: meson-gx: fix i2c compatible
arm64: dts: meson-gx: cec node should be disabled by default
arm64: dts: meson-g12b-odroid-n2: add missing amlogic, s922x compatible
arm64: dts: meson-gxm: fix gpu irq order
arm64: dts: meson-g12a: fix gpu irq order
...
|
||
|
Linus Torvalds
|
ec939e4c94 |
ARM: SoC-related driver updates
Various driver updates for platforms:
- A larger set of work on Tegra 2/3 around memory controller and
regulator features, some fuse cleanups, etc..
- MMP platform drivers, in particular for USB PHY, and other smaller
additions.
- Samsung Exynos 5422 driver for DMC (dynamic memory configuration),
and ASV (adaptive voltage), allowing the platform to run at more
optimal operating points.
- Misc refactorings and support for RZ/G2N and R8A774B1 from Renesas
- Clock/reset control driver for TI/OMAP
- Meson-A1 reset controller support
- Qualcomm sdm845 and sda845 SoC IDs for socinfo
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Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC driver updates from Olof Johansson:
"Various driver updates for platforms:
- A larger set of work on Tegra 2/3 around memory controller and
regulator features, some fuse cleanups, etc..
- MMP platform drivers, in particular for USB PHY, and other smaller
additions.
- Samsung Exynos 5422 driver for DMC (dynamic memory configuration),
and ASV (adaptive voltage), allowing the platform to run at more
optimal operating points.
- Misc refactorings and support for RZ/G2N and R8A774B1 from Renesas
- Clock/reset control driver for TI/OMAP
- Meson-A1 reset controller support
- Qualcomm sdm845 and sda845 SoC IDs for socinfo"
* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (150 commits)
firmware: arm_scmi: Fix doorbell ring logic for !CONFIG_64BIT
soc: fsl: add RCPM driver
dt-bindings: fsl: rcpm: Add 'little-endian' and update Chassis definition
memory: tegra: Consolidate registers definition into common header
memory: tegra: Ensure timing control debug features are disabled
memory: tegra: Introduce Tegra30 EMC driver
memory: tegra: Do not handle error from wait_for_completion_timeout()
memory: tegra: Increase handshake timeout on Tegra20
memory: tegra: Print a brief info message about EMC timings
memory: tegra: Pre-configure debug register on Tegra20
memory: tegra: Include io.h instead of iopoll.h
memory: tegra: Adapt for Tegra20 clock driver changes
memory: tegra: Don't set EMC rate to maximum on probe for Tegra20
memory: tegra: Add gr2d and gr3d to DRM IOMMU group
memory: tegra: Set DMA mask based on supported address bits
soc: at91: Add Atmel SFR SN (Serial Number) support
memory: atmel-ebi: switch to SPDX license identifiers
memory: atmel-ebi: move NUM_CS definition inside EBI driver
soc: mediatek: Refactor bus protection control
soc: mediatek: Refactor sram control
...
|
||
|
Olof Johansson
|
5588aa81d2 |
arm64: dts: Amlogic updates for v5.5
Hightlights - new board; ugoos am6, based on G12B SoC - g12: add thermal driver and cooling properties - sm1: enable audio on SEI610 board - IR: add several keymaps - sdio: add keep-power-in-suspend property for multiple boards - pcie: add support for G12A - multiple fixes, cleanups -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEe4dGDhaSf6n1v/EMWTcYmtP7xmUFAl3FFnEACgkQWTcYmtP7 xmWyeg//QE6hBYYjZfwiIbLCgRlpdv04HZg6e5bPqZ8A9x9/mdQoH6cqwbKVpKij bLrkHuwD+WtkWStbemdPtmPliEncAyX9jXGcvIor3eYa9IV6kTORZ8YWq6c8RDMM y8UafRFbt24MNvzi41uuUoSLtlsLUDp6dVfekD4wf1IvV7Ew5Yk5XyHMAjdVongC 07FA1aY6JOiPZeDcvNa11pxlzyciDf22YF8XLoZOsZ/cZN1itjBUMqGRefC51RQP cafmdk0Ms+Xgtq4GwDceLE5QMb/h1K582j4uVu38QMpPqR6WvTnpd/ra4chheJHE nhHHYiN4mWO3lgnp1ZZKooTUyBPAyf3kaP8I7YBrUXuuoy9GNRqKi25uJwALeVqh YKvZqpd6Uw4W/If5EW5zPXlKGv8xSJwaTh6q40sRI0OFMfniy1pLRM3mLKSVqJy6 DKk7Pt4wptWe6Bv6P1hK34acmX6TGcyq53Dg5Nq79E0qul1YRRmHoUHewOeUgwPC XSaaqPSItLQggRXplZVaUm9e8cmjcwU4Od3rqfb/A2JsTniONB3kAI6YoBCsK4O2 SwCbIVP8hkbCo/perun11C4SnsamPdQBmPs1if8PtT72LaNR8HAlFZTgX5yqEFAj ZP9vCgqtdlIE28W9cJLOEMT7KtAzCES2UYbKUDTx+E2GolvoYvA= =pQlU -----END PGP SIGNATURE----- Merge tag 'amlogic-dt64' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/dt arm64: dts: Amlogic updates for v5.5 Hightlights - new board; ugoos am6, based on G12B SoC - g12: add thermal driver and cooling properties - sm1: enable audio on SEI610 board - IR: add several keymaps - sdio: add keep-power-in-suspend property for multiple boards - pcie: add support for G12A - multiple fixes, cleanups * tag 'amlogic-dt64' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: (62 commits) arm64: dts: meson-gx: fix i2c compatible arm64: dts: meson-gx: cec node should be disabled by default arm64: dts: meson-g12b-odroid-n2: add missing amlogic, s922x compatible arm64: dts: meson-gxm: fix gpu irq order arm64: dts: meson-g12a: fix gpu irq order ARM64: dts: amlogic: adds crypto hardware node arm64: dts: meson-gxbb-vega-s95: set rc-vega-s9x ir keymap arm64: dts: meson-gxm-vega-s96: set rc-vega-s9x ir keymap arm64: dts: meson: g12b: add cooling properties arm64: dts: meson: g12a: add cooling properties arm64: dts: meson: g12: Add minimal thermal zone arm64: dts: meson: g12: add temperature sensor arm64: dts: meson: sei610: enable audio arm64: dts: meson: sm1: add audio devices dt-bindings: clock: meson: add sm1 resets to the axg-audio controller dt-bindings: clk: axg-audio: add sm1 bindings arm64: dts: meson-g12: add support for simplefb arm64: dts: meson: g12a: add audio devices resets arm64: dts: meson: odroid-c2: Add missing regulator linked to HDMI supply arm64: dts: meson: odroid-c2: Add missing regulator linked to VDDIO_AO3V3 regulator ... Link: https://lore.kernel.org/r/7hd0dzs0m1.fsf@baylibre.com Signed-off-by: Olof Johansson <olof@lixom.net> |
||
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Andreas Färber
|
4df56a1eb1 |
dt-bindings: reset: Add Realtek RTD1295
Add a header with symbolic reset indices for Realtek RTD1295 SoC. Naming was derived from reset-names in an OEM's Device Tree. Acked-by: Rob Herring <robh@kernel.org> [AF: Dropped RTD1295 specific binding definition, updated SPDX] Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Andreas Färber <afaerber@suse.de> |
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Kevin Hilman
|
f21ab7906d |
First round of amlogic DT binding clock update target for v5.5
Add the audio clock and reset bindings for the sm1 SoC family -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE9OFZrhjz9W1fG7cb5vwPHDfy2oUFAl2cO+cACgkQ5vwPHDfy 2oXQug//cqVN9hhMgZv+an1DmZbJ2vt2lJvs9ddk2eNodlLC3wvz93YeNyqNn79p 11KNDBtgaorR5o41wfjHSlqZBqQQjhIPKdod/i5xzAJSi/0d6GzahrcUp6jXsE5o dzImQcGXzhhYpK21JXftq3OBqwEQrML5DgW+ab42IoV8CERCDSavpn/ZYP2RRqBY +5n1owpW+2f5xp2fkT5T/HGrDEdAbgM3lZEgM4w/2Tp9XpBxHDqbS7iDV7OLV+4/ Mb4zXwB9ra7u/bxEIPi4tpUaruZYfNFd5c3lWOd6nD+218UHo2pF0ZLlaNhw3Xdp 0M9Cyjy5hgqPDWTfmVKkKQKWXY7ys06rvLXowAfaob0SpHKV11QtPnmJYhsmDP60 vQTwi1ejfl/KsmNm6b6OTuRdflRCuDVueUuuX1xIFc30phnoqt99pvjz8GVSzqiX rx3QdYvhXbi0ioqSjdiu8KITBjdllsfPpO42qMsnU5wOWeOLQk9Ju42yK9IFwjSs C5aDeo9WEaUHYHJpI+KXdB38BFDEv2qvKz729t/tnenmgq0F+gy1CUPtwIe0rP8J GxK/KEEgCuwuwL/LcSb9iA7U2ycmDE0G6Kqoh0kTQd698CeIvPiLy9+yNP5HZeyT 2eUFGpKGSyZ25P5SAIHkQ2PSScjsQ5wemsf1jFuJgn/dngPEDkM= =XPSR -----END PGP SIGNATURE----- Merge tag 'clk-meson-dt-v5.5-1' of git://github.com/BayLibre/clk-meson into v5.5/dt64-redo First round of amlogic DT binding clock update target for v5.5 Add the audio clock and reset bindings for the sm1 SoC family * tag 'clk-meson-dt-v5.5-1' of git://github.com/BayLibre/clk-meson: dt-bindings: clock: meson: add sm1 resets to the axg-audio controller dt-bindings: clk: axg-audio: add sm1 bindings |
||
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Xingyu Chen
|
5d9730b9eb |
dt-bindings: reset: add bindings for the Meson-A1 SoC Reset Controller
Add DT bindings for the Meson-A1 SoC Reset Controller include file, and also slightly update documentation. Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> |
||
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Jerome Brunet
|
aa03ea9bce |
dt-bindings: clock: meson: add sm1 resets to the axg-audio controller
Add the reset id of the sm1 audio clock controller Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> |
||
|
Jerome Brunet
|
c2016cc612 |
reset: dt-bindings: meson: update arb bindings for sm1
SM1 SoC family adds two new audio FIFOs with the related arb reset lines Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> |
||
|
Linus Torvalds
|
a703d279c5 |
We have a small collection of core framework updates this time, mostly around
clk registration by clk providers and debugfs "nice to haves" for rate constraints. I'll highlight that we're now setting the clk_init_data pointer inside struct clk_hw to NULL during clk_register(), which may break some drivers that thought they could use that pointer during normal operations. That change has been sitting in next for a while now but maybe something is still broken. We'l see. Other than that the core framework changes aren't invasive and they're fixing bugs, simplifying, and making things better. On the clk driver side we got the usual addition of new SoC support, new features for existing drivers, and bug fixes scattered throughout. The biggest diffstat is the Amlogic driver that gained CPU clk support in addition to migrating to the new way of specifying clk parents. After that the Qualcomm, i.MX, Mediatek, and Rockchip clk drivers got support for various new SoCs and clock controllers from those vendors. Core: - Drop NULL checks in clk debugfs - Add min/max rates to clk debugfs - Set clk_init_data pointer inside clk_hw to NULL after registration - Make clk_bulk_get_all() return an 'id' corresponding to clock-names - Evict parents from parent cache when they're unregistered New Drivers: - Add clock driver for i.MX8MN SoCs - Support aspeed AST2600 SoCs - Support for Mediatek MT6779 SoCs - Support qcom SM8150 GCC and RPMh clks - Support qcom QCS404 WCSS clks - Add CPU clock support for Armada 7K/8K (specifically AP806 and AP807) - Addition of clock driver for Rockchip rk3308 SoCs Updates: - Add regulator support to the cdce925 clk driver - Add support for Raspberry Pi 4 bcm2711 SoCs - Add SDIO gate support to aspeed driver - Add missing of_node_put() calls in various clk drivers - Migrate Amlogic driver to new clock parent description method - Add DVFS support to Amlogic Meson g12 - Add Amlogic Meson g12a reset support to the axg audio clock controller - Add sm1 support to the Amlogic Meson g12a clock controller - Switch i.MX8MM clock driver to platform driver - Add Hifi4 DSP related clocks for i.MX8QXP SoC - Fix Audio PLL setting and parent clock for USB - Misc i.MX8 clock driver improvements and corrections - Set floor ops for Qualcomm SD clks so that rounding works - Fix "always-on" Clock Domains on Renesas R-Car M1A, RZ/A1, RZ/A2, and RZ/N1 - Enable the Allwinner V3 SoC and fix the i2s clock for H6 -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAl2FQEMRHHNib3lkQGtl cm5lbC5vcmcACgkQrQKIl8bklSXHQw//XHnT5DPphpP8ua4x8wuJARdf0n58Vcdb 8fZxxs4QN7uuKhg6aMI4kgwBn+9tgIr65hvN0Gn9Wm5Bsbs3XZvdIo7DvQDrYg7W NE7192iy2Dg+m+C24YLO7ceZgqVepbjeN+6oeUK88Ui+H+XlOKfJvjfnJ+HxN9Ip sHnLakIxqlaWvzwTUOHOcsrHyQD2OXupbfNMxLnmr8T/kBh/nqwNEG3aYCppICsg LpJL9Bv2V3QSk8uBszTgKK5ybWo14aDQPx4rrhgsneD0h7DSnx6M3jvngxMra6W0 fnare4FQlkbPmgAj+XtB7RdCzsuwoke/7TJsvDLQrEbyOYTGnl7bYS8NOSrIg5Tp w4UPpXrMTQK7e/6okL1OJYAXXYurxep8QjsjpF3nahxC3IVzAZ9uio6ehJrDNEPC ErqOSPQTMkjOA2npovsQKCH3Mv/yGzAigpsQassPneWwp//NupMLKmmIm6645Xw2 6kqSlVFYz81lhzIylGEQKIoiLcszpB6qqWUzGVt0B94joRbvg0m//8BDaZbHeTqP m/acRYHRC1utpkAZEnBZRsd79cI+EeuARROUfGsoUMfOueTc4+qQ7Yrjbj4rTvnC lLM9Qz9h1QkfyRF1IHHPw/fS5twpNTUdO9c1+3qzS3AQfl5dZWpChoF9Um+ycVPR nQrpk05pHEY= =z8wK -----END PGP SIGNATURE----- Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "We have a small collection of core framework updates this time, mostly around clk registration by clk providers and debugfs "nice to haves" for rate constraints. I'll highlight that we're now setting the clk_init_data pointer inside struct clk_hw to NULL during clk_register(), which may break some drivers that thought they could use that pointer during normal operations. That change has been sitting in next for a while now but maybe something is still broken. We'l see. Other than that the core framework changes aren't invasive and they're fixing bugs, simplifying, and making things better. On the clk driver side we got the usual addition of new SoC support, new features for existing drivers, and bug fixes scattered throughout. The biggest diffstat is the Amlogic driver that gained CPU clk support in addition to migrating to the new way of specifying clk parents. After that the Qualcomm, i.MX, Mediatek, and Rockchip clk drivers got support for various new SoCs and clock controllers from those vendors. Core: - Drop NULL checks in clk debugfs - Add min/max rates to clk debugfs - Set clk_init_data pointer inside clk_hw to NULL after registration - Make clk_bulk_get_all() return an 'id' corresponding to clock-names - Evict parents from parent cache when they're unregistered New Drivers: - Add clock driver for i.MX8MN SoCs - Support aspeed AST2600 SoCs - Support for Mediatek MT6779 SoCs - Support qcom SM8150 GCC and RPMh clks - Support qcom QCS404 WCSS clks - Add CPU clock support for Armada 7K/8K (specifically AP806 and AP807) - Addition of clock driver for Rockchip rk3308 SoCs Updates: - Add regulator support to the cdce925 clk driver - Add support for Raspberry Pi 4 bcm2711 SoCs - Add SDIO gate support to aspeed driver - Add missing of_node_put() calls in various clk drivers - Migrate Amlogic driver to new clock parent description method - Add DVFS support to Amlogic Meson g12 - Add Amlogic Meson g12a reset support to the axg audio clock controller - Add sm1 support to the Amlogic Meson g12a clock controller - Switch i.MX8MM clock driver to platform driver - Add Hifi4 DSP related clocks for i.MX8QXP SoC - Fix Audio PLL setting and parent clock for USB - Misc i.MX8 clock driver improvements and corrections - Set floor ops for Qualcomm SD clks so that rounding works - Fix "always-on" Clock Domains on Renesas R-Car M1A, RZ/A1, RZ/A2, and RZ/N1 - Enable the Allwinner V3 SoC and fix the i2s clock for H6" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (137 commits) clk: Drop !clk checks in debugfs dumping clk: imx: imx8mn: fix pll mux bit clk: imx: imx8mm: fix pll mux bit clk: imx: clk-pll14xx: unbypass PLL by default clk: imx: pll14xx: avoid glitch when set rate clk: mvebu: ap80x: add AP807 clock support clk: mvebu: ap806: Prepare the introduction of AP807 clock support clk: mvebu: ap806: add AP-DCLK (hclk) to system controller driver clk: mvebu: ap806: be more explicit on what SaR is clk: mvebu: ap80x-cpu: add AP807 CPU clock support clk: mvebu: ap806-cpu: prepare mapping of AP807 CPU clock dt-bindings: ap806: Document AP807 clock compatible dt-bindings: ap80x: Document AP807 CPU clock compatible clk: sprd: add missing kfree clk: at91: allow 24 Mhz clock as input for PLL clk: Make clk_bulk_get_all() return a valid "id" clk: actions: Fix factor clk struct member access clk: qcom: rcg: Return failure for RCG update clk: remove extra ---help--- tags in Kconfig clk: add include guard to clk-conf.h ... |
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Stephen Boyd
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a1ff1ce300 |
Merge branches 'clk-init-destroy', 'clk-doc', 'clk-imx' and 'clk-allwinner' into clk-next
- Set clk_init_data pointer inside clk_hw to NULL after registration * clk-init-destroy: clk: Overwrite clk_hw::init with NULL during clk_register() clk: sunxi: Don't call clk_hw_get_name() on a hw that isn't registered clk: ti: Don't reference clk_init_data after registration clk: qcom: Remove error prints from DFS registration rtc: sun6i: Don't reference clk_init_data after registration clk: zx296718: Don't reference clk_init_data after registration clk: milbeaut: Don't reference clk_init_data after registration clk: socfpga: deindent code to proper indentation phy: ti: am654-serdes: Don't reference clk_init_data after registration clk: sprd: Don't reference clk_init_data after registration clk: socfpga: Don't reference clk_init_data after registration clk: sirf: Don't reference clk_init_data after registration clk: qcom: Don't reference clk_init_data after registration clk: meson: axg-audio: Don't reference clk_init_data after registration clk: lochnagar: Don't reference clk_init_data after registration clk: actions: Don't reference clk_init_data after registration * clk-doc: clk: remove extra ---help--- tags in Kconfig clk: add include guard to clk-conf.h clk: Document of_parse_clkspec() some more clk: Remove extraneous 'for' word in comments * clk-imx: (32 commits) clk: imx: imx8mn: fix pll mux bit clk: imx: imx8mm: fix pll mux bit clk: imx: clk-pll14xx: unbypass PLL by default clk: imx: pll14xx: avoid glitch when set rate clk: imx: imx8mn: fix audio pll setting clk: imx8mn: Add necessary frequency support for ARM PLL table clk: imx8mn: Add missing rate_count assignment for each PLL structure clk: imx8mn: fix int pll clk gate clk: imx8mn: Add GIC clock clk: imx8mn: Fix incorrect parents clk: imx8mm: Fix incorrect parents clk: imx8mq: Fix sys3 pll references clk: imx8mq: Unregister clks when of_clk_add_provider failed clk: imx8mm: Unregister clks when of_clk_add_provider failed clk: imx8mq: Mark AHB clock as critical clk: imx8mn: Keep uart clocks on for early console clk: imx: Remove unused function statement clk: imx7ulp: Make sure earlycon's clock is enabled clk: imx8mm: Switch to platform driver clk: imx: imx8mm: fix audio pll setting ... * clk-allwinner: clk: sunxi-ng: h6: Allow I2S to change parent rate clk: sunxi-ng: v3s: add Allwinner V3 support clk: sunxi-ng: v3s: add missing clock slices for MMC2 module clocks dt-bindings: clk: sunxi-ccu: add compatible string for V3 CCU clk: sunxi-ng: v3s: add the missing PLL_DDR1 |
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Linus Torvalds
|
e3a008ac12 |
Devicetree updates for v5.4:
- A bunch of DT binding conversions to DT schema format - Clean-ups of the Arm idle-states binding - Support a default number of cells in of_for_each_phandle() when the cells name is missing - Expose dtbs_check and dt_binding_check in the make help - Convert writting-schema.md to ReST - HiSilicon reset controller binding updates - Add documentation for MT8516 RNG -----BEGIN PGP SIGNATURE----- iQJEBAABCgAuFiEEktVUI4SxYhzZyEuo+vtdtY28YcMFAl2Dj38QHHJvYmhAa2Vy bmVsLm9yZwAKCRD6+121jbxhw4qcEACE16/eR0h9FSnhN0QpyFlGrfUTy86K5Z4N IoJsGind4G7+TrNA6GGZwQkNRt3roWdrkqnLLvcted+8IVaXOFm0n12w2u0yoYvk C4pqxH2HRUC9U9eBjyDxdiplH9yYZPuy8bFwLPSQk0bkCd6D3I8iDe6qHm1arin3 sYIQ03jbZKowHixOuMNvu9rBiun79Lm5FfGUSi7EYab3KZ4Zt9HX1IiySRYVOWZT z6bjWbVfFe7HgbImwaB+WUYumUyNu5dh4AyqIidb9o6BB6ZENfnBNWPi0VDFuSGT 4wVc8XrcU3d7bt6Sstt+g3WZjn+JBMLNBkNnMjZ+nlp3OoR5F6Tf1RO6mrZtsENa sAspr18zNQK7CNBy0uKzBT32Z0oN1wXnsKRS5P1o5/8aEjRr0m8stxes3hOQhtuJ Y6rKLN9kGrQIeSY7nagWuGFaJ1uunGXCSgam+kb6YI8nDa3DUbzeIhYMIcqgz/Sx Gx2txPzKMHXgzF7Zc+5db9X3E7pg8Y1zrhk7o2oKiFVWrnwlEJivMcRHq9n3anOr RGAJPjrRfzwZNIQgYNflYHAdxVLyKKhpxEQDdo/5PXeMRYtghOH+rIxwoS31FHSs u/4nf0uHFQfkmSg7nSKicfSWt5ORR5G/H9cc83SRoix35kfPubirkawJ/tkcVuO4 3n0NeGERtA== =ZO6c -----END PGP SIGNATURE----- Merge tag 'devicetree-for-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux Pull Devicetree updates from Rob Herring: - a bunch of DT binding conversions to DT schema format - clean-ups of the Arm idle-states binding - support a default number of cells in of_for_each_phandle() when the cells name is missing - expose dtbs_check and dt_binding_check in the make help - convert writting-schema.md to ReST - HiSilicon reset controller binding updates - add documentation for MT8516 RNG * tag 'devicetree-for-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (46 commits) of: restore old handling of cells_name=NULL in of_*_phandle_with_args() bus: qcom: fix spelling mistake "ambigous" -> "ambiguous" of: Let of_for_each_phandle fallback to non-negative cell_count iommu: pass cell_count = -1 to of_for_each_phandle with cells_name dt-bindings: arm: Convert Realtek board/soc bindings to json-schema dt-bindings: arm: Convert Actions Semi bindings to jsonschema dt-bindings: Correct spelling in example schema dt-bindings: cpu: Add a support cpu type for cortex-a55 dt-bindings: gpu: mali-midgard: Add samsung exynos5250 compatible dt-bindings: arm: idle-states: Move exit-latency-us explanation dt-bindings: arm: idle-states: Add punctuation to improve readability dt-bindings: arm: idle-states: Correct "constraint guarantees" dt-bindings: arm: idle-states: Correct references to wake-up delay dt-bindings: arm: idle-states: Use "e.g." and "i.e." consistently pinctrl-mcp23s08: Fix property-name in dt-example dt-bindings: Clarify interrupts-extended usage dt-bindings: Convert Arm Mali Utgard GPU to DT schema dt-bindings: Convert Arm Mali Bifrost GPU to DT schema dt-bindings: Convert Arm Mali Midgard GPU to DT schema dt-bindings: irq: Convert Allwinner NMI Controller to a schema ... |
||
|
Linus Torvalds
|
cef7298262 |
ARM: DT updates for v5.4
This is another huge branch with close to 450 changessets related to
devicetree files, roughly half of this for 32-bit and 64-bit respectively.
There are lots of cleanups and additional hardware support for platforms
we already support based on SoCs from Renesas, ST-Microelectronics,
Intel/Altera, Rockchips, Allwinner, Broadcom and other manufacturers.
A total of 6 new SoCs and 37 new boards gets added this time, one more
SoC will come in a follow-up branch. Most of the new boards are for
64-bit ARM SoCs, the others are typically for the 32-bit Cortex-A7.
Going more into details for SoC platforms with new hardware support:
The Snapdragon 855 (SM8150) is Qualcomm's current high-end phone platform,
usually paired with an external 5G modem. So far we only support the
Qualcomm SM8150 MTP reference platform, but no actual products.
For the slightly older Qualcomm platforms, support for several interesting
products is getting added: Three laptops based on Snapdragon 835/MSM8998
(Asus NovaGo, HP Envy X2 and Lenovo Miix 630), one laptop based on
Snapdragon 850/sdm850 (Lenovo Yoga C630) and several phones based on
the older Snapdragon 410/MSM8916 (Samsung A3 and A5, Longcheer L8150
aka Android One 2nd gen "seed" aka Wileyfox Swift).
Mediatek MT7629 is a new wireless network router chip, similar to
the older MT7623. It gets added together with the reference board
implementation.
Allwinner V3 is a repackaged version of the existing low-end V3s chip,
and is used in the tiny Lichee Pi Zero plus, also added here. There is
also a new TV set-top box based on Allwinner H6, the Tanix TX6, and the
eMMC variant of the Olimex A64-Olinuxino development board.
NXP i.MX8M Nano is a new member of the ever-expanding i.MX SoC family,
similar to the i.MX8M Mini. As usual, there is a large number of new
boards for i.MX SoCs: Einfochips i.MX8QXP AI_ML, SolidRun Hummingboard
Pulse baseboard and System-on-Module, Boundary Devices i.MX8MQ Nitrogen8M,
and TechNexion PICO-PI-IMX8M-DEV for the 64-bit i.MX8 line. For 32-bit,
we get the Kontron i.MX6UL N6310 SoM with two baseboards, the PHYTEC
phyBOARD-Segin SoM with three baseboards, and the Zodiac Inflight
Innovations i.MX7 RMU2 board.
In a different NXP product line, the Layerscape LS1046A "Freeway"
reference board gets added.
Amlogic SM1 (S905X3) and G12B (S922X, A311D) are updated chips from their
set-top-box line and smart speaker with newer CPU and GPU cores compared
to their predecessors. Both are now also supported by the Khadas VIM3
development board series, and the dts files for that get reorganized a
bit to better deal with all variants. Another board based on SM1 that
gets added is the SEI Robotics SEI610.
There are a handful of new x86 and Power9 server boards using Aspeed BMC
chips that are gaining support for running Linux on the BMC through the
OpenBMC project: Facebook Minipack/Wedge100/Wedge40, Lenovo Hr855xg2,
and Mihawk. Notably these are still new machines using SoCs based on
the ARM9 and ARM11 CPU cores, as support for the new Cortex-A7 based
AST2600 is still ramping up.
There are three new end-user products using 32-bit Rockchips SoCs:
Mecer Xtreme Mini S6 is an Android "mini PC" box based on the low-end
RK3229 chip, while the two AOpen products Chromebox Mini (Fievel) and
Chromebase Mini (Tiger) run ChromeOS and are meant for commercial settings
(digital signage, PoS, ...).
One more single-board computer based on the popular 64-bit RK3399 is
added: the Leez RK3399 P710.
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM DT updates from Arnd Bergmann:
"This is another huge branch with close to 450 changessets related to
devicetree files, roughly half of this for 32-bit and 64-bit
respectively. There are lots of cleanups and additional hardware
support for platforms we already support based on SoCs from Renesas,
ST-Microelectronics, Intel/Altera, Rockchips, Allwinner, Broadcom and
other manufacturers.
A total of 6 new SoCs and 37 new boards gets added this time, one more
SoC will come in a follow-up branch. Most of the new boards are for
64-bit ARM SoCs, the others are typically for the 32-bit Cortex-A7.
Going more into details for SoC platforms with new hardware support:
- The Snapdragon 855 (SM8150) is Qualcomm's current high-end phone
platform, usually paired with an external 5G modem. So far we only
support the Qualcomm SM8150 MTP reference platform, but no actual
products.
- For the slightly older Qualcomm platforms, support for several
interesting products is getting added: Three laptops based on
Snapdragon 835/MSM8998 (Asus NovaGo, HP Envy X2 and Lenovo Miix
630), one laptop based on Snapdragon 850/sdm850 (Lenovo Yoga C630)
and several phones based on the older Snapdragon 410/MSM8916
(Samsung A3 and A5, Longcheer L8150 aka Android One 2nd gen "seed"
aka Wileyfox Swift).
- Mediatek MT7629 is a new wireless network router chip, similar to
the older MT7623. It gets added together with the reference board
implementation.
- Allwinner V3 is a repackaged version of the existing low-end V3s
chip, and is used in the tiny Lichee Pi Zero plus, also added here.
There is also a new TV set-top box based on Allwinner H6, the Tanix
TX6, and the eMMC variant of the Olimex A64-Olinuxino development
board.
- NXP i.MX8M Nano is a new member of the ever-expanding i.MX SoC
family, similar to the i.MX8M Mini. As usual, there is a large
number of new boards for i.MX SoCs: Einfochips i.MX8QXP AI_ML,
SolidRun Hummingboard Pulse baseboard and System-on-Module,
Boundary Devices i.MX8MQ Nitrogen8M, and TechNexion
PICO-PI-IMX8M-DEV for the 64-bit i.MX8 line. For 32-bit, we get the
Kontron i.MX6UL N6310 SoM with two baseboards, the PHYTEC
phyBOARD-Segin SoM with three baseboards, and the Zodiac Inflight
Innovations i.MX7 RMU2 board.
- In a different NXP product line, the Layerscape LS1046A "Freeway"
reference board gets added.
- Amlogic SM1 (S905X3) and G12B (S922X, A311D) are updated chips from
their set-top-box line and smart speaker with newer CPU and GPU
cores compared to their predecessors. Both are now also supported
by the Khadas VIM3 development board series, and the dts files for
that get reorganized a bit to better deal with all variants.
Another board based on SM1 that gets added is the SEI Robotics
SEI610.
- There are a handful of new x86 and Power9 server boards using
Aspeed BMC chips that are gaining support for running Linux on the
BMC through the OpenBMC project: Facebook
Minipack/Wedge100/Wedge40, Lenovo Hr855xg2, and Mihawk. Notably
these are still new machines using SoCs based on the ARM9 and ARM11
CPU cores, as support for the new Cortex-A7 based AST2600 is still
ramping up.
- There are three new end-user products using 32-bit Rockchips SoCs:
Mecer Xtreme Mini S6 is an Android "mini PC" box based on the
low-end RK3229 chip, while the two AOpen products Chromebox Mini
(Fievel) and Chromebase Mini (Tiger) run ChromeOS and are meant for
commercial settings(digital signage, PoS, ...).
- One more single-board computer based on the popular 64-bit RK3399
is added: the Leez RK3399 P710"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (467 commits)
arm64: dts: qcom: Add Lenovo Yoga C630
ARM: dts: aspeed-g5: Fixe gpio-ranges upper limit
ARM; dts: aspeed: mihawk: File should not be executable
ARM: dts: aspeed: swift: Change power supplies to version 2
ARM: dts: aspeed: vesnin: Add secondary SPI flash chip
ARM: dts: aspeed: vesnin: Add wdt2 with alt-boot option
ARM: dts: aspeed-g4: Add all flash chips
ARM: dts: exynos: Enable GPU/Mali T604 on Arndale board
ARM: dts: exynos: Enable GPU/Mali T604 on Chromebook Snow
ARM: dts: exynos: Add GPU/Mali T604 node to Exynos5250
ARM: dts: exynos: Fix min/max buck4 for GPU on Arndale board
ARM: dts: exynos: Mark LDO10 as always-on on Peach Pit/Pi Chromebooks
ARM: dts: exynos: Remove not accurate secondary ADC compatible
arm64: dts: rockchip: limit clock rate of MMC controllers for RK3328
arm64: dts: meson-sm1-sei610: add stdout-path property back
arm64: dts: meson-sm1-sei610: enable DVFS
arm64: dts: khadas-vim3: add support for the SM1 based VIM3L
dt-bindings: arm: amlogic: add Amlogic SM1 based Khadas VIM3L bindings
arm64: dts: khadas-vim3: move common nodes into meson-khadas-vim3.dtsi
arm64: dts: meson: g12a: add reset to tdm formatters
...
|
||
|
Arnd Bergmann
|
f02bd65a5b |
arm64: dts: Amlogic updates for v5.4 (round 2)
- new board: Khadas VIM3L (SM1/S905D3 SoC) - support power domains on G12[AB] and SM1 SoCs - DT binding fixups based on YAML schema - add a bunch of remote control keymap - enable DVFS on SM1/SEI610 board -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEe4dGDhaSf6n1v/EMWTcYmtP7xmUFAl1oX4gACgkQWTcYmtP7 xmVgmA//bj9MUuKJYgXJ6ZSdtSFK7tL3MwqMmwJpt8PPRt+KTUEr3x6Ix+ZvkpYB YsiUYvA0URIL5gcibsIP6UsO6c0QAwnW6NaWGl96cHPwGAB6cBdWY5msxHEC6KaN GzBOjlsTTv1gFptz9vLd8RvEXeH/M92pdIwWQrIE1c9LXKfLoLhC5dHlw9iHG7kN ja7Qsv9J3GkuTPYoPh04X2q44NPGwUtxhMNqGbn9S9T5YCqXkKa4RWgyvs/Iam72 hs/humUMdlciH4pSFikKQd0Xouf2cYnEIsVqWFuHFgDs5KuYrSlOAutVgkcFOcnb bG61iKV5urue0sxnar8Fx0OR6aeT04A9zGHWEPH6Tq2kfl5VQNZUKZb5XUZJWgWe vj0kTG6L7wk5oem19TtHOTZTpwRTdk3Bkth+dt9RZtmVC/HL1C79Fkt1BKpCYesQ 7tsUmNnTprz0unUQIbY6UMfzpD8JixGM/ak5ODJ+pQivFlbgu/eQTDNRAOsEjszn w7AZtyp2AANJN/u5Vxf8IqonOzF1UhMyrIa39D6vAQn0xfCMlFh0RcV5Afs4qows GRJ17JMVL7da/cbyoG17gCyQSYYTWPkPIbqOEyUOTqOzEGVgHweNsBOWBkEwolNv v0+rIJHjw11527ibqdBxMIKIrSIfhN63j343zN0RrwMdZbHroJg= =7yjy -----END PGP SIGNATURE----- Merge tag 'amlogic-dt64-2.1' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/dt arm64: dts: Amlogic updates for v5.4 (round 2) - new board: Khadas VIM3L (SM1/S905D3 SoC) - support power domains on G12[AB] and SM1 SoCs - DT binding fixups based on YAML schema - add a bunch of remote control keymap - enable DVFS on SM1/SEI610 board * tag 'amlogic-dt64-2.1' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: (44 commits) arm64: dts: meson-sm1-sei610: add stdout-path property back arm64: dts: meson-sm1-sei610: enable DVFS arm64: dts: khadas-vim3: add support for the SM1 based VIM3L dt-bindings: arm: amlogic: add Amlogic SM1 based Khadas VIM3L bindings arm64: dts: khadas-vim3: move common nodes into meson-khadas-vim3.dtsi arm64: dts: meson: g12a: add reset to tdm formatters arm64: dts: meson: g12a: audio clock controller provides resets arm64: dts: meson-sm1-sei610: enable DVFS arm64: dts: meson-gxm-khadas-vim2: use rc-khadas keymap arm64: dts: meson-gxl-s905w-tx3-mini: add rc-tx3mini keymap arm64: dts: meson-gxl-s905x-khadas-vim: use rc-khadas keymap arm64: dts: meson-gxbb-wetek-play2: add rc-wetek-play2 keymap arm64: dts: meson-gxbb-wetek-hub: add rc-wetek-hub keymap arm64: dts: meson-g12a-x96-max: add rc-x96max keymap arm64: dts: meson-g12b-odroid-n2: add rc-odroid keymap arm64: dts: meson-sm1-sei610: add USB support arm64: dts: meson-sm1-sei610: add HDMI display support arm64: dts: meson-g12: add Everything-Else power domain controller arm64: dts: meson: fix boards regulators states format arm64: dts: meson-gxbb-p201: fix snps, reset-delays-us format ... Link: https://patchwork.kernel.org/patch/11122331/ Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
||
|
Ryder Lee
|
cc212241df |
arm: dts: mediatek: add basic support for MT7629 SoC
This adds basic support for MT7629 reference board. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> |
||
|
Peter Griffin
|
5f912f7ced |
dt-bindings: reset: hisilicon: Add ao reset controller
This is required to bring Mali450 gpu out of reset. Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Philipp Zabel <p.zabel@pengutronix.de> Cc: dri-devel@lists.freedesktop.org Cc: devicetree@vger.kernel.org Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: John Stultz <john.stultz@linaro.org> Signed-off-by: Rob Herring <robh@kernel.org> |
||
|
Jerome Brunet
|
0688587a71 |
dt-bindings: clock: meson: add resets to the audio clock controller
Add the documentation and bindings for the resets provided by the g12a audio clock controller Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> |
||
|
Icenowy Zheng
|
0ed4c252bf
|
clk: sunxi-ng: v3s: add Allwinner V3 support
Allwinner V3 has the same main die with V3s, but with more pins wired. There's a I2S bus on V3 that is not available on V3s. Add the V3-only peripheral's clocks and reset to the V3s CCU driver, bound to a new V3 compatible string. The driver name is not changed because it's part of the device tree binding (the header file name). Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> |
||
|
Neil Armstrong
|
fb0d72c7ac |
dt-bindings: reset: amlogic,meson8b-reset: update with SPDX Licence identifier
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> |
||
|
Neil Armstrong
|
b16a006365 |
dt-bindings: reset: amlogic,meson-gxbb-reset: update with SPDX Licence identifier
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> |
||
|
Guido Günther
|
942b4c10b1 |
dt-bindings: reset: Fix typo in imx8mq resets
Some of the mipi dsi resets were called IMX8MQ_RESET_MIPI_DIS__ instead of IMX8MQ_RESET_MIPI_DSI__ Since they're DSI related this looks like a typo. This fixes the only in tree user as well to not break bisecting. Signed-off-by: Guido Günther <agx@sigxcpu.org> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> |
||
|
Anson Huang
|
e2557157a9 |
dt-bindings: reset: imx7: Add support for i.MX8MM
i.MX8MM can reuse i.MX8MQ's reset driver, update the compatible property and related info to support i.MX8MM. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> |
||
|
Olof Johansson
|
8c0993621c |
Reset controller changes for v5.3
This tag adds support for the Bitmain BM1880 reset controller to the reset-simple driver and fixes a spelling mistake in the i.MX7 reset controller binding document. -----BEGIN PGP SIGNATURE----- iI0EABYIADUWIQRRO6F6WdpH1R0vGibVhaclGDdiwAUCXR3SoxcccC56YWJlbEBw ZW5ndXRyb25peC5kZQAKCRDVhaclGDdiwEb6AP4i9FSRodn9AFs8jKcgUC63SPyL L5loesyFpiTVpunMsQEAlexZ6wSY2zdfVrDXh1lLHmuACc8AuebItcdpaRwc3As= =Zp5w -----END PGP SIGNATURE----- Merge tag 'reset-for-v5.3' of git://git.pengutronix.de/git/pza/linux into arm/drivers Reset controller changes for v5.3 This tag adds support for the Bitmain BM1880 reset controller to the reset-simple driver and fixes a spelling mistake in the i.MX7 reset controller binding document. * tag 'reset-for-v5.3' of git://git.pengutronix.de/git/pza/linux: dt-bindings: reset: imx7: Fix the spelling of 'indices' reset: Add reset controller support for BM1880 SoC dt-bindings: reset: Add devicetree binding for BM1880 reset controller Link: https://lore.kernel.org/r/1562236632.6641.14.camel@pengutronix.de Signed-off-by: Olof Johansson <olof@lixom.net> |
||
|
Thomas Gleixner
|
9c92ab6191 |
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 282
Based on 1 normalized pattern(s): this software is licensed under the terms of the gnu general public license version 2 as published by the free software foundation and may be copied distributed and modified under those terms this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 285 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190529141900.642774971@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
||
|
Thomas Gleixner
|
9952f6918d |
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms and conditions of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 228 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Steve Winslow <swinslow@gmail.com> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190528171438.107155473@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
||
|
Thomas Gleixner
|
1802d0beec |
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 655 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Richard Fontana <rfontana@redhat.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070034.575739538@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
||
|
Thomas Gleixner
|
c942fddf87 |
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157
Based on 3 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version [author] [kishon] [vijay] [abraham] [i] [kishon]@[ti] [com] this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version [author] [graeme] [gregory] [gg]@[slimlogic] [co] [uk] [author] [kishon] [vijay] [abraham] [i] [kishon]@[ti] [com] [based] [on] [twl6030]_[usb] [c] [author] [hema] [hk] [hemahk]@[ti] [com] this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 1105 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070033.202006027@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
||
|
Manivannan Sadhasivam
|
ef98682a4e |
dt-bindings: reset: Add devicetree binding for BM1880 reset controller
Add devicetree binding for Bitmain BM1880 SoC reset controller. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> |
||
|
Neil Armstrong
|
a6256b3a92 |
dt-bindings: reset: meson-g12a: Add missing USB2 PHY resets
The G12A Documentation lacked these 2 reset lines, but they are present and
used for each USB 2 PHYs.
Add them to the dt-bindings for the upcoming USB support.
Fixes:
|
||
|
Linus Torvalds
|
dc2535be1f |
We have a fairly balanced mix of clk driver updates and clk framework
updates this time around. It's the usual pile of new drivers for new
hardware out there and the normal small fixes and updates, but then we
have some core framework changes too.
In the core framework, we introduce support for a clk_get_optional() API
to get clks that may not always be populated and a way to devm manage clkdev
lookups registered by provider drivers. We also do some refactoring to simplify
the interface between clkdev and the common clk framework so we can reuse the DT
parsing and clk_get() path in provider drivers in the future. This work will
continue in the next few cycles while we convert how providers specify clk
parents.
On the driver side, the biggest part of the dirstat is the Amlogic clk driver
that got support for the G12A SoC. It dominates with almost half the overall
diff, while the second largest part of the diff is in the i.MX clk driver
that gained support for imx8mm SoCs. After that, we have the Actions Semiconductor
and Qualcomm drivers rounding out the big part of the dirstat because they both
got new hardware support for SoCs. The rest is just various updates and non-critical
fixes for existing drivers.
Core:
- Convert a few clk bindings to JSON schema format
- Add a {devm_}clk_get_optional() API
- Add devm_clk_hw_register_clkdev() API to manage clkdev lookups
- Start rewriting clk parent registration and supporting device links
by moving around code that supports clk_get() and DT parsing of the
'clocks' property
New Drivers:
- Add Qualcomm MSM8998 RPM managed clks
- IPA clk support on Qualcomm RPMh clk controllers
- Actions Semi S500 SoC clk support
- Support for fixed rate clks populated from an MMIO register
- Add RPC (QSPI/HyperFLASH) clocks on Renesas R-Car V3H
- Add TMU (timer) clocks on Renesas RZ/G2E
- Add Amlogic G12A Always-On Clock Controller
- Add 32k clock generation for Amlogic AXG
- Add support for the Mali GPU clocks on Amlogic Meson8
- Add Amlogic G12A EE clock controller driver
- Add missing CANFD clocks on Renesas RZ/G2M and RZ/G2E
- Add i.MX8MM SoC clk driver support
Removed Drivers:
- Remove clps711x driver as the board support is gone
Updates:
- 3rd ECO fix for Mediatek MT2712 SoCs
- Updates for Qualcomm MSM8998 GCC clks
- Random static analysis fixes for clk drivers
- Support for sleeping gpios in the clk-gpio type
- Minor fixes for STM32MP1 clk driver (parents, critical flag, etc.)
- Split LCDC into two clks on the Marvell MMP2 SoC
- Various DT of_node refcount fixes
- Get rid of CLK_IS_BASIC from TI code (yay!)
- TI Autoidle clk support
- Fix Amlogic Meson8 APB clock ID name
- Claim input clocks through DT for Amlogic AXG and GXBB
- Correct the DU (display unit) parent clock on Renesas RZ/G2E
- Exynos5433 IMEM CMU crypto clk support (SlimSS)
- Fix for the PLL-MIPI on the Allwinner A23
- Fix Rockchip rk3328 PLL rate calculation
- Add SET_RATE_PARENT flag on display clk of Rockhip rk3066
- i.MX SCU clk driver clk_set_parent() and cpufreq support
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk subsystem updates from Stephen Boyd:
"We have a fairly balanced mix of clk driver updates and clk framework
updates this time around. It's the usual pile of new drivers for new
hardware out there and the normal small fixes and updates, but then we
have some core framework changes too.
In the core framework, we introduce support for a clk_get_optional()
API to get clks that may not always be populated and a way to devm
manage clkdev lookups registered by provider drivers. We also do some
refactoring to simplify the interface between clkdev and the common
clk framework so we can reuse the DT parsing and clk_get() path in
provider drivers in the future. This work will continue in the next
few cycles while we convert how providers specify clk parents.
On the driver side, the biggest part of the dirstat is the Amlogic clk
driver that got support for the G12A SoC. It dominates with almost
half the overall diff, while the second largest part of the diff is in
the i.MX clk driver that gained support for imx8mm SoCs. After that,
we have the Actions Semiconductor and Qualcomm drivers rounding out
the big part of the dirstat because they both got new hardware support
for SoCs. The rest is just various updates and non-critical fixes for
existing drivers.
Core:
- Convert a few clk bindings to JSON schema format
- Add a {devm_}clk_get_optional() API
- Add devm_clk_hw_register_clkdev() API to manage clkdev lookups
- Start rewriting clk parent registration and supporting device links
by moving around code that supports clk_get() and DT parsing of the
'clocks' property
New Drivers:
- Add Qualcomm MSM8998 RPM managed clks
- IPA clk support on Qualcomm RPMh clk controllers
- Actions Semi S500 SoC clk support
- Support for fixed rate clks populated from an MMIO register
- Add RPC (QSPI/HyperFLASH) clocks on Renesas R-Car V3H
- Add TMU (timer) clocks on Renesas RZ/G2E
- Add Amlogic G12A Always-On Clock Controller
- Add 32k clock generation for Amlogic AXG
- Add support for the Mali GPU clocks on Amlogic Meson8
- Add Amlogic G12A EE clock controller driver
- Add missing CANFD clocks on Renesas RZ/G2M and RZ/G2E
- Add i.MX8MM SoC clk driver support
Removed Drivers:
- Remove clps711x driver as the board support is gone
Updates:
- 3rd ECO fix for Mediatek MT2712 SoCs
- Updates for Qualcomm MSM8998 GCC clks
- Random static analysis fixes for clk drivers
- Support for sleeping gpios in the clk-gpio type
- Minor fixes for STM32MP1 clk driver (parents, critical flag, etc.)
- Split LCDC into two clks on the Marvell MMP2 SoC
- Various DT of_node refcount fixes
- Get rid of CLK_IS_BASIC from TI code (yay!)
- TI Autoidle clk support
- Fix Amlogic Meson8 APB clock ID name
- Claim input clocks through DT for Amlogic AXG and GXBB
- Correct the DU (display unit) parent clock on Renesas RZ/G2E
- Exynos5433 IMEM CMU crypto clk support (SlimSS)
- Fix for the PLL-MIPI on the Allwinner A23
- Fix Rockchip rk3328 PLL rate calculation
- Add SET_RATE_PARENT flag on display clk of Rockhip rk3066
- i.MX SCU clk driver clk_set_parent() and cpufreq support"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (150 commits)
dt-bindings: clock: imx8mq: Fix numbering overlaps and gaps
clk: ti: clkctrl: Fix clkdm_name regression for TI_CLK_CLKCTRL_COMPAT
clk: fixup default index for of_clk_get_by_name()
clk: Move of_clk_*() APIs into clk.c from clkdev.c
clk: Inform the core about consumer devices
clk: Introduce of_clk_get_hw_from_clkspec()
clk: core: clarify the check for runtime PM
clk: Combine __clk_get() and __clk_create_clk()
clk: imx8mq: add GPIO clocks to clock tree
clk: mediatek: correct cpu clock name for MT8173 SoC
clk: imx: Refactor entire sccg pll clk
clk: imx: scu: add cpu frequency scaling support
clk: mediatek: Mark bus and DRAM related clocks as critical
clk: mediatek: Add flags to mtk_gate
clk: mediatek: Add MUX_FLAGS macro
clk: qcom: gcc-sdm845: Define parent of PCIe PIPE clocks
clk: ingenic: Remove set but not used variable 'enable'
clk: at91: programmable: remove unneeded register read
clk: mediatek: using CLK_MUX_ROUND_CLOSEST for the clock of dpi1_sel
clk: mediatek: add MUX_GATE_FLAGS_2
...
|
||
|
Stephen Boyd
|
3f8e7e7247 |
Merge branches 'clk-optional', 'clk-devm-clkdev-register', 'clk-allwinner', 'clk-meson' and 'clk-renesas' into clk-next
- Add a {devm_}clk_get_optional() API
- Add devm_clk_hw_register_clkdev() API to manage clkdev lookups
* clk-optional:
clk: Add (devm_)clk_get_optional() functions
clk: Add comment about __of_clk_get_by_name() error values
* clk-devm-clkdev-register:
clk: clk-st: avoid clkdev lookup leak at remove
clk: clk-max77686: Clean clkdev lookup leak and use devm
clkdev: add managed clkdev lookup registration
* clk-allwinner:
clk: sunxi-ng: sun8i-a23: Enable PLL-MIPI LDOs when ungating it
* clk-meson: (22 commits)
clk: meson: meson8b: fix the naming of the APB clocks
dt-bindings: clock: meson8b: add APB clock definition
clk: meson: Add G12A AO Clock + Reset Controller
dt-bindings: clk: add G12A AO Clock and Reset Bindings
clk: meson: factorise meson64 peripheral clock controller drivers
clk: meson: g12a: add peripheral clock controller
dt-bindings: clk: meson: add g12a periph clock controller bindings
clk: meson: pll: update driver for the g12a
clk: meson: rework and clean drivers dependencies
clk: meson: axg-audio does not require syscon
clk: meson: use CONFIG_ARCH_MESON to enter meson clk directory
clk: export some clk_hw function symbols for module drivers
clk: meson: ao-clkc: claim clock controller input clocks from DT
clk: meson: axg: claim clock controller input clock from DT
clk: meson: gxbb: claim clock controller input clock from DT
clk: meson: meson8b: add the GPU clock tree
clk: meson: meson8b: use a separate clock table for Meson8
clk: meson: axg-ao: add 32k generation subtree
clk: meson: gxbb-ao: replace cec-32k with the dual divider
clk: meson: add dual divider clock driver
...
* clk-renesas:
clk: renesas: r8a774a1: Fix LAST_DT_CORE_CLK
clk: renesas: r8a774c0: Fix LAST_DT_CORE_CLK
clk: renesas: r8a774c0: Add TMU clock
clk: renesas: r8a77980: Add RPC clocks
clk: renesas: rcar-gen3: Add RPC clocks
clk: renesas: rcar-gen3: Add spinlock
clk: renesas: rcar-gen3: Factor out cpg_reg_modify()
clk: renesas: r8a774c0: Correct parent clock of DU
clk: renesas: r8a774a1: Add missing CANFD clock
clk: renesas: r8a774c0: Add missing CANFD clock
|
||
|
Arnd Bergmann
|
6f2185f8e3 |
Reset controller changes for v5.1
This adds the include/linux/reset directory to MAINTAINERS for reset specific headers and adds headers for sunxi and socfpga in there to get rid of a few extern function declarations. There is a new reset driver for the Broadcom STB reset controller and the i.MX7 system reset controller driver is extended to support i.MX8MQ as well. Finally, there is a new header with reset id constants for the Meson G12A SoC, which has a reset controller identical to Meson AXG and thus can reuse its driver and DT bindings. -----BEGIN PGP SIGNATURE----- iI0EABYIADUWIQRRO6F6WdpH1R0vGibVhaclGDdiwAUCXF2yeRcccC56YWJlbEBw ZW5ndXRyb25peC5kZQAKCRDVhaclGDdiwH8jAP9OQaMl5llVXuHSFOwiqkJ2I09p oROxu3dI/A4q7d5T8QD/Xuo4piSAdoT5YZyHp16NUafW3L1//wqTvxk0ubeTsgA= =EIyo -----END PGP SIGNATURE----- Merge tag 'reset-for-5.1' of git://git.pengutronix.de/git/pza/linux into arm/drivers Reset controller changes for v5.1 This adds the include/linux/reset directory to MAINTAINERS for reset specific headers and adds headers for sunxi and socfpga in there to get rid of a few extern function declarations. There is a new reset driver for the Broadcom STB reset controller and the i.MX7 system reset controller driver is extended to support i.MX8MQ as well. Finally, there is a new header with reset id constants for the Meson G12A SoC, which has a reset controller identical to Meson AXG and thus can reuse its driver and DT bindings. * tag 'reset-for-5.1' of git://git.pengutronix.de/git/pza/linux: dt-bindings: reset: meson: add g12a bindings reset: imx7: Add support for i.MX8MQ IP block variant reset: imx7: Add plubming to support multiple IP variants reset: Add Broadcom STB SW_INIT reset controller driver dt-bindings: reset: Add document for Broadcom STB reset controller reset: socfpga: declare socfpga_reset_init in a header file reset: sunxi: declare sun6i_reset_init in a header file MAINTAINERS: use include/linux/reset for reset controller related headers dt-bindings: reset: imx7: Document usage on i.MX8MQ SoCs Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
||
|
Arnd Bergmann
|
59f527dd7a |
arm64: zynqmp: SoC changes for v5.1
- Extend firmware interface with reset, nvmem, power management and power domain support - Add reset, nvmem driver, power management and power domain drivers - -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iEYEABECAAYFAlxixLEACgkQykllyylKDCEduwCeLkIFr48uJ/5Fv1X16gitcrOk F38An2wbsk21xkWQpfzCFdUrpPbT0u4t =GOP8 -----END PGP SIGNATURE----- Merge tag 'zynqmp-soc-for-v5.1' of https://github.com/Xilinx/linux-xlnx into arm/drivers arm64: zynqmp: SoC changes for v5.1 - Extend firmware interface with reset, nvmem, power management and power domain support - Add reset, nvmem driver, power management and power domain drivers - * tag 'zynqmp-soc-for-v5.1' of https://github.com/Xilinx/linux-xlnx: drivers: soc: xilinx: Add ZynqMP power domain driver firmware: xilinx: Add APIs to control node status/power dt-bindings: power: Add ZynqMP power domain bindings drivers: soc: xilinx: Add ZynqMP PM driver firmware: xilinx: Implement ZynqMP power management APIs dt-bindings: soc: Add ZynqMP PM bindings nvmem: zynqmp: Added zynqmp nvmem firmware driver dt-bindings: nvmem: Add bindings for ZynqMP nvmem driver firmware: xilinx: Add zynqmp_pm_get_chipid() API reset: reset-zynqmp: Adding support for Xilinx zynqmp reset controller. dt-bindings: reset: Add bindings for ZynqMP reset driver firmware: xilinx: Add reset API's Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
||
|
Neil Armstrong
|
be3d960b0a |
dt-bindings: clk: add G12A AO Clock and Reset Bindings
Add bindings for the Amlogic G12A AO Clock and Reset controllers. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lkml.kernel.org/r/20190212162859.20743-2-narmstrong@baylibre.com |
||
|
Jerome Brunet
|
dbfc54534d |
dt-bindings: reset: meson: add g12a bindings
Add device tree bindings for the reset controller of g12a SoC family. Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> |
||
|
Nava kishore Manne
|
3f1b66be4a |
dt-bindings: reset: Add bindings for ZynqMP reset driver
Add documentation to describe Xilinx ZynqMP reset driver bindings. Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
||
|
Andrey Smirnov
|
4cab5bf616 |
dt-bindings: reset: imx7: Document usage on i.MX8MQ SoCs
The driver now supports i.MX8MQ, so update bindings accordingly. Cc: p.zabel@pengutronix.de Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: cphealy@gmail.com Cc: l.stach@pengutronix.de Cc: Leonard Crestez <leonard.crestez@nxp.com> Cc: "A.s. Dong" <aisheng.dong@nxp.com> Cc: Richard Zhu <hongxing.zhu@nxp.com> Cc: linux-imx@nxp.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> |
||
|
Jerome Brunet
|
3705add0b7 |
dt-bindings: reset: meson-axg: fix SPDX license id
As reported, the SPDX license id is not placed correctly and the variant
of the BSD License used should be specified.
Fixes:
|
||
|
Mesih Kilinc
|
3d737ddbe7
|
dt-bindings: clock: Add Allwinner suniv F1C100s CCU
Add compatiple string for Allwinner suniv F1C100s CCU. Add clock and reset definitions. Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> |
||
|
Jernej Skrabec
|
b9f9e9b8e4
|
dt-bindings: clock: sun8i-de2: Add H6 DE3 clock description
This commit adds necessary description and dt includes for H6 DE3 clock. It is very similar to others, but memory region has some additional registers not found in DE2. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> |
||
|
Linus Torvalds
|
519f64bf15 |
This time it looks like a quieter release cycle in the clk tree. I guess that's
because of summer time holidays/vacations. The biggest change in the diffstat is in the Qualcomm clk driver, where they got support for CPUs and handful of SoCs. After that, the at91 driver got a major rewrite for newer DT bindings that should make things easier going forward and the TI code moved to a clockdomain based design. The long tail is mostly small driver updates for newer clks and some simpler SoC clock drivers such as the Hisilicon and imx support. In the core framework, we only have two small changes this time. One is a new clk API to get all clks for a device with the bulk clk APIs. This allows drivers that don't care about doing anything besides turning on all the clks to just clk_get() them all and turn them on. The other change is the beginning of a way to support save and restore of clk settings in the clk framework. TI is the only user right now, but we will want to expand upon this design in the future to support more save and restore of clk registers. At least this gets us started and works well enough for one SoC, but there's more work in the future. Core: - clk_bulk_get_all() API and friends to get all the clks for a device - Basic clk state save/restore hooks New Drivers: - Renesas RZ/A2 (R7S9210) SoC, including early clocks - Rensas RZ/G1N (R8A7744) and RZ/G2E (R8A774C0) SoCs - Rensas RZ/G2M (r8a774a1) SoC - Qualcomm Krait CPU clk support - Qualcomm QCS404 GCC support - Qualcomm SDM660 GCC support - Qualcomm SDM845 camera clock controller - Ingenic jz4725b CGU - Hisilicon 3670 SoC support - TI SCI clks on K3 SoCs - iMX6 MMDC clks - Reset Controller (RMU) support for Actions Semi Owl S900 and S700 SoCs Updates: - Rework at91 PMC clock driver for new DT bindings - Nvidia Tegra clk driver MBIST workaround fix - S2RAM support for Marvell mvebu periph clks - Use updated printk format for OF node names - Fix TI code to only search DT subnodes - Various static analysis finds - Tag various drivers with SPDX license tags - Support dynamic frequency switching (DFS) on qcom SDM845 GCC - Only use s2mps11 dt-binding defines instead of redefining them in the driver - Add some more missing clks to qcom MSM8996 GCC - Quad SPI clks on qcom SDM845 - Add support for CMT timer clocks on R-Car V3H - Add support for SHDI and various timer clocks on R-Car V3M - Improve OSC and RCLK (watchdog) handling on R-Car Gen3 SoCs - Amlogic clk-pll driver improvements and updates - Amlogic axg audio controller system clocks - Register Amlogic meson8b clock controller early - Add support for SATA and Fine Display Processor (FDP) clocks on R-Car M3-N - Consolidation of system suspend related code in Exynos, S5P, S3C SoC clk drivers - Fixes for system suspend support on Exynos542x (Odroid boards) and Exynos5433 SoC - Remove obsoleted Exynos4212 ISP clock definitions - Migrated TI am3/4/5 and dra7 SoCs to clockdomain based design - TI RTC+DDR sleep mode support for clock save/restore - Allwinner A64 display engine support and fixes - Allwinner A83t display engine support and fixes -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAlvY4ysRHHNib3lkQGtl cm5lbC5vcmcACgkQrQKIl8bklSVaDBAA3Wv/rsCn4FJ2ZgIWYWQqr69lAWDcBVVe 4nNbFqzEmRoml8e+XOfVFwnbsai4B5ALVxyMnRlkDyxQ5TFQtF957U12Pf8upPa5 R447YBt4tw40NCj8u5KNAaBmYYHdmXXDvsBPXyQn+1iy/9R8Is8AcDmv+D2ucuJF PPBXOwb+2CstUQhuwlXyvsAw/tqq/rJDVyAZVJUoqXJwlNMjr76V0m0ZXHN6NcyC F2SfnzIO4srRteTeKXVFcMU/3uHC3zofEfammSJjGZkk4WHULuPpkD17RMEyBul1 Ju1S1nzGiKvYME/mmbIcRPNcpry65EVo/wn6IjAcG2m4GaWSq3F6qIttnoc6dnra R2VylIEy7HnNcAf8fkQdkd/l+h/TDp3iVrXg0p/rRxRk4Jlc86n2PWO6jtsZv4S+ NySeRhTb51KrTl72J76LP+dfDWdbeZfkAqr0Qx6QM04OznVYSTHlnQaeM1Nx2SZR 5+k126NdxDp7xgoJNfq18wzufrlefjuRTg2Kck1YuFuhV4Fjmq7ZC81bSSaakYPh /t073TcSZ+VfEYP5hVsl/pjMdFzHcj8pbavhs0UNIYLQNXe494Bm9PyYJOzQKnwz Zpbf7V6eplh8J1I03VI8RHviNp340iv2hhz9vp4mNP1vIhgdNiz7R2gn5sLSoFt+ vei0J0vEzCA= =V5aK -----END PGP SIGNATURE----- Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "This time it looks like a quieter release cycle in the clk tree. I guess that's because of summer time holidays/vacations. The biggest change in the diffstat is in the Qualcomm clk driver, where they got support for CPUs and handful of SoCs. After that, the at91 driver got a major rewrite for newer DT bindings that should make things easier going forward and the TI code moved to a clockdomain based design. The long tail is mostly small driver updates for newer clks and some simpler SoC clock drivers such as the Hisilicon and imx support. In the core framework, we only have two small changes this time. One is a new clk API to get all clks for a device with the bulk clk APIs. This allows drivers that don't care about doing anything besides turning on all the clks to just clk_get() them all and turn them on. The other change is the beginning of a way to support save and restore of clk settings in the clk framework. TI is the only user right now, but we will want to expand upon this design in the future to support more save and restore of clk registers. At least this gets us started and works well enough for one SoC, but there's more work in the future. Core: - clk_bulk_get_all() API and friends to get all the clks for a device - Basic clk state save/restore hooks New Drivers: - Renesas RZ/A2 (R7S9210) SoC, including early clocks - Rensas RZ/G1N (R8A7744) and RZ/G2E (R8A774C0) SoCs - Rensas RZ/G2M (r8a774a1) SoC - Qualcomm Krait CPU clk support - Qualcomm QCS404 GCC support - Qualcomm SDM660 GCC support - Qualcomm SDM845 camera clock controller - Ingenic jz4725b CGU - Hisilicon 3670 SoC support - TI SCI clks on K3 SoCs - iMX6 MMDC clks - Reset Controller (RMU) support for Actions Semi Owl S900 and S700 SoCs Updates: - Rework at91 PMC clock driver for new DT bindings - Nvidia Tegra clk driver MBIST workaround fix - S2RAM support for Marvell mvebu periph clks - Use updated printk format for OF node names - Fix TI code to only search DT subnodes - Various static analysis finds - Tag various drivers with SPDX license tags - Support dynamic frequency switching (DFS) on qcom SDM845 GCC - Only use s2mps11 dt-binding defines instead of redefining them in the driver - Add some more missing clks to qcom MSM8996 GCC - Quad SPI clks on qcom SDM845 - Add support for CMT timer clocks on R-Car V3H - Add support for SHDI and various timer clocks on R-Car V3M - Improve OSC and RCLK (watchdog) handling on R-Car Gen3 SoCs - Amlogic clk-pll driver improvements and updates - Amlogic axg audio controller system clocks - Register Amlogic meson8b clock controller early - Add support for SATA and Fine Display Processor (FDP) clocks on R-Car M3-N - Consolidation of system suspend related code in Exynos, S5P, S3C SoC clk drivers - Fixes for system suspend support on Exynos542x (Odroid boards) and Exynos5433 SoC - Remove obsoleted Exynos4212 ISP clock definitions - Migrated TI am3/4/5 and dra7 SoCs to clockdomain based design - TI RTC+DDR sleep mode support for clock save/restore - Allwinner A64 display engine support and fixes - Allwinner A83t display engine support and fixes" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (186 commits) clk: qcom: Remove unused arrays in SDM845 GCC clk: fixed-rate: fix of_node_get-put imbalance clk: s2mps11: Add used attribute to s2mps11_dt_match clk: qcom: gcc-sdm660: Add MODULE_LICENSE clk: qcom: Add safe switch hook for krait mux clocks dt-bindings: clock: Document qcom,krait-cc clk: qcom: Add Krait clock controller driver dt-bindings: arm: Document qcom,kpss-gcc clk: qcom: Add KPSS ACC/GCC driver clk: qcom: Add support for Krait clocks clk: qcom: Add IPQ806X's HFPLLs clk: qcom: Add MSM8960/APQ8064's HFPLLs dt-bindings: clock: Document qcom,hfpll clk: qcom: Add HFPLL driver clk: qcom: Add support for High-Frequency PLLs (HFPLLs) ARM: Add Krait L2 register accessor functions clk: imx6q: add mmdc0 ipg clock clk: imx6sl: add mmdc ipg clocks clk: imx6sll: add mmdc1 ipg clock clk: imx6sx: add mmdc1 ipg clock ... |
||
|
Linus Torvalds
|
b22b6beae6 |
ARM: SoC driver updates for 4.17
The most noteworthy SoC driver changes this time include:
- The TEE subsystem gains an in-kernel interface to access the TEE
from device drivers.
- The reset controller subsystem gains a driver for the Qualcomm
Snapdragon 845 Power Domain Controller.
- The Xilinx Zynq platform now has a firmware interface for its
platform management unit. This contains a firmware "ioctl" interface
that was a little controversial at first, but the version we merged
solved that by not exposing arbitrary firmware calls to user space.
- The Amlogic Meson platform gains a "canvas" driver that is used
for video processing and shared between different high-level drivers.
The rest is more of the usual, mostly related to SoC specific power
management support and core drivers in drivers/soc:
- Several Renesas SoCs (RZ/G1N, RZ/G2M, R-Car V3M, RZ/A2M) gain new
features related to power and reset control.
- The Mediatek mt8183 and mt6765 SoC platforms gain support for
their respective power management chips.
- A new driver for NXP i.MX8, which need a firmware interface for
power management.
- The SCPI firmware interface now contains support estimating power
usage of performance states
- The NVIDIA Tegra "pmc" driver gains a few new features, in particular
a pinctrl interface for configuring the pads.
- Lots of small changes for Qualcomm, in particular the "smem"
device driver.
- Some cleanups for the TI OMAP series related to their sysc
controller.
Additional cleanups and bugfixes in SoC specific drivers include the
Meson, Keystone, NXP, AT91, Sunxi, Actions, and Tegra platforms.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver updates from Arnd Bergmann:
"The most noteworthy SoC driver changes this time include:
- The TEE subsystem gains an in-kernel interface to access the TEE
from device drivers.
- The reset controller subsystem gains a driver for the Qualcomm
Snapdragon 845 Power Domain Controller.
- The Xilinx Zynq platform now has a firmware interface for its
platform management unit. This contains a firmware "ioctl"
interface that was a little controversial at first, but the version
we merged solved that by not exposing arbitrary firmware calls to
user space.
- The Amlogic Meson platform gains a "canvas" driver that is used for
video processing and shared between different high-level drivers.
The rest is more of the usual, mostly related to SoC specific power
management support and core drivers in drivers/soc:
- Several Renesas SoCs (RZ/G1N, RZ/G2M, R-Car V3M, RZ/A2M) gain new
features related to power and reset control.
- The Mediatek mt8183 and mt6765 SoC platforms gain support for their
respective power management chips.
- A new driver for NXP i.MX8, which need a firmware interface for
power management.
- The SCPI firmware interface now contains support estimating power
usage of performance states
- The NVIDIA Tegra "pmc" driver gains a few new features, in
particular a pinctrl interface for configuring the pads.
- Lots of small changes for Qualcomm, in particular the "smem" device
driver.
- Some cleanups for the TI OMAP series related to their sysc
controller.
Additional cleanups and bugfixes in SoC specific drivers include the
Meson, Keystone, NXP, AT91, Sunxi, Actions, and Tegra platforms"
* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (129 commits)
firmware: tegra: bpmp: Implement suspend/resume support
drivers: clk: Add ZynqMP clock driver
dt-bindings: clock: Add bindings for ZynqMP clock driver
firmware: xilinx: Add zynqmp IOCTL API for device control
Documentation: xilinx: Add documentation for eemi APIs
MAINTAINERS: imx: include drivers/firmware/imx path
firmware: imx: add misc svc support
firmware: imx: add SCU firmware driver support
reset: Fix potential use-after-free in __of_reset_control_get()
dt-bindings: arm: fsl: add scu binding doc
soc: fsl: qbman: add interrupt coalesce changing APIs
soc: fsl: bman_portals: defer probe after bman's probe
soc: fsl: qbman: Use last response to determine valid bit
soc: fsl: qbman: Add 64 bit DMA addressing requirement to QBMan
soc: fsl: qbman: replace CPU 0 with any online CPU in hotplug handlers
soc: fsl: qbman: Check if CPU is offline when initializing portals
reset: qcom: PDC Global (Power Domain Controller) reset controller
dt-bindings: reset: Add PDC Global binding for SDM845 SoCs
reset: Grammar s/more then once/more than once/
bus: ti-sysc: Just use SET_NOIRQ_SYSTEM_SLEEP_PM_OPS
...
|
||
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Manivannan Sadhasivam
|
a35bcf7c7f |
dt-bindings: reset: Add binding constants for Actions Semi S900 RMU
Add device tree binding constants for Actions Semi S900 SoC Reset Management Unit (RMU). Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> |
||
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Manivannan Sadhasivam
|
73a5e67efa |
dt-bindings: reset: Add binding constants for Actions Semi S700 RMU
Add device tree binding constants for Actions Semi S700 SoC Reset Management Unit (RMU). Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> |
||
|
Leonard Crestez
|
de24832709 |
reset: imx7: Add PCIE_CTRL_APPS_TURNOFF
This is required for the imx pci driver to send the PME_Turn_Off TLP. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Rob Herring <robh@kernel.org> |
||
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Sibi Sankar
|
032f11638f |
dt-bindings: reset: Add PDC Global binding for SDM845 SoCs
Add PDC Global (Power Domain Controller) binding for SDM845 SoCs. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> |
||
|
Jerome Brunet
|
5338073561 |
reset: meson: add dt-bindings for meson-axg audio arb
Add dt-bindings for the audio memory arbiter found on Amlogic's A113 based SoCs Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> |
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Sibi Sankar
|
b79df1ec22 |
dt-bindings: reset: Add AOSS reset bindings for SDM845 SoCs
Add SDM845 AOSS (always on subsystem) reset controller binding Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> |
||
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Stephen Boyd
|
b2ac878acd |
Merge branches 'clk-davinci-psc-da830', 'clk-renesas', 'clk-at91-recalc', 'clk-davinci' and 'clk-meson' into clk-next
* clk-davinci-psc-da830: clk: davinci: psc-da830: fix USB0 48MHz PHY clock registration * clk-renesas: clk: renesas: cpg-mssr: Add support for R-Car E3 clk: renesas: Add r8a77990 CPG Core Clock Definitions clk: renesas: rcar-gen2: Centralize quirks handling clk: renesas: r8a77980: Correct parent clock of PCIEC0 clk: renesas: r8a7794: Fix LB clock divider clk: renesas: r8a7792: Fix LB clock divider clk: renesas: r8a7791/r8a7793: Fix LB clock divider clk: renesas: r8a7745: Fix LB clock divider clk: renesas: r8a7743: Fix LB clock divider clk: renesas: cpg-mssr: Add r8a77470 support clk: renesas: Add r8a77470 CPG Core Clock Definitions clk: renesas: r8a77965: Add MSIOF controller clocks * clk-at91-recalc: clk: at91: PLL recalc_rate() now using cached MUL and DIV values * clk-davinci: clk: davinci: Fix link errors when not all SoCs are enabled clk: davinci: psc: allow for dev == NULL clk: davinci: da850-pll: change PLL0 to CLK_OF_DECLARE clk: davinci: pll: allow dev == NULL clk: davinci: psc-dm365: fix few clocks clk: davinci: pll-dm646x: keep PLL2 SYSCLK1 always enabled clk: davinci: psc-dm355: fix ASP0/1 clkdev lookups clk: davinci: pll-dm355: fix SYSCLKn parent names clk: davinci: pll-dm355: drop pll2_sysclk2 * clk-meson: clk: meson: axg: let mpll clocks round closest clk: meson: mpll: add round closest support clk: meson: meson8b: mark fclk_div2 gate clocks as CLK_IS_CRITICAL clk: meson: use SPDX license identifiers consistently clk: meson: drop CLK_SET_RATE_PARENT flag clk: meson-axg: Add AO Clock and Reset controller driver clk: meson: aoclk: refactor common code into dedicated file clk: meson: migrate to devm_of_clk_add_hw_provider API clk: meson: gxbb: add the video decoder clocks clk: meson: meson8b: add support for the NAND clocks dt-bindings: clock: reset: Add AXG AO Clock and Reset Bindings dt-bindings: clock: axg-aoclkc: New binding for Meson-AXG SoC clk: meson: gxbb: expose VDEC_1 and VDEC_HEVC clocks dt-bindings: clock: meson8b: export the NAND clock |
||
|
Stephen Boyd
|
45ba387511 |
Merge branches 'clk-allwinner', 'clk-rockchip', 'clk-tegra', 'clk-berlin' and 'clk-qcom-mmagic' into clk-next
* clk-allwinner: clk: sunxi-ng: r40: export a regmap to access the GMAC register clk: sunxi-ng: r40: rewrite init code to a platform driver clk: sunxi-ng: add support for H6 PRCM CCU * clk-rockchip: clk: rockchip: remove deprecated gate-clk code and dt-binding clk: rockchip: use match_string() helper * clk-tegra: clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20 clk: tegra20: Correct parents of CDEV1/2 clocks clk: tegra20: Add DEV1/DEV2 OSC dividers * clk-berlin: clk: berlin: switch to SPDX license identifier * clk-qcom-mmagic: clk: qcom: mmcc-msm8996: leave all mmagic gdscs and clocks always enabled clk: qcom: Register the gdscs before the clocks clk: qcom: gdsc: Add support for ALWAYS_ON gdscs |
||
|
Sean Wang
|
5eb57e1e7a |
dt-bindings: reset: mediatek: add entry for Mali-450 node to refer
Just add binding for a required reset referenced by Mali-450 on MT7623 or MT2701 SoC. Cc: devicetree@vger.kernel.org Signed-off-by: Sean Wang <sean.wang@mediatek.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> |
||
|
Yixun Lan
|
9c7aea8e17 |
dt-bindings: clock: reset: Add AXG AO Clock and Reset Bindings
Add dt-bindings headers for the Meson-AXG's AO clock and reset controller. Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> |
||
|
Icenowy Zheng
|
b7c7b05065 |
clk: sunxi-ng: add support for H6 PRCM CCU
The H6 has clock/reset controls in PRCM part, like old SoCs such as H3 and A64. However, the PRCM CCU is rearranged; the register arragement is now similar to the main CCU of H6, and the PRCM now has two APB buses to control -- one is clocked from AHB clock derivde from AR100 clock, the other is clocked from the same mux with AR100 clock. Therefore a new driver is written for it. As there's no official document about the PRCM in H6, all the information are indirectly collected from BSP and parts of the document, and the information source is noted as comments in the driver's source code. If reliable information is provided furtherly, the driver needs to be rechecked. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> |
||
|
Linus Torvalds
|
ca4e7c5120 |
The large diff this time around is from the addition of a new clk driver
for the TI Davinci family of SoCs. So far those clks have been supported with a custom implementation of the clk API in the arch port instead of in the CCF. With this driver merged we're one step closer to having a single clk API implementation. The other large diff is from the Amlogic clk driver that underwent some major surgery to use regmap. Beyond that, the biggest hitter is Samsung which needed some reworks to properly handle clk provider power domains and a bunch of PLL rate updates. The core framework was fairly quiet this round, just getting some cleanups and small fixes for some of the more esoteric features. And the usual set of driver non-critical fixes, cleanups, and minor additions are here as well. Core: - Rejig clk_ops::init() to be a little earlier for phase/accuracy ops - debugfs ops macroized to shave some lines of boilerplate code - Always calculate the phase instead of caching it in clk_get_phase() - More __must_check on bulk clk APIs New Drivers: - TI's Davinci family of SoCs - Intel's Stratix10 SoC - stm32mp157 SoC - Allwinner H6 CCU - Silicon Labs SI544 clock generator chip - Renesas R-Car M3-N and V3H SoCs - i.MX6SLL SoCs Removed Drivers: - ST-Ericsson AB8540/9540 Updates: - Mediatek MT2701 and MT7622 audsys support and MT2712 updates - STM32F469 DSI and STM32F769 sdmmc2 support - GPIO clks can sleep now - Spreadtrum SC9860 RTC clks - Nvidia Tegra MBIST workarounds and various minor fixes - Rockchip phase handling fixes and a memory leak plugged - Renesas drivers switch to readl/writel from clk_readl/clk_writel - Renesas gained CPU (Z/Z2) and watchdog support - Rockchip rk3328 display clks and rk3399 1.6GHz PLL support - Qualcomm PM8921 PMIC XO buffers - Amlogic migrates to regmap APIs - TI Keystone clk latching support - Allwinner H3 and H5 video clk fixes - Broadcom BCM2835 PLLs needed another bit to enable - i.MX6SX CKO mux fix and i.MX7D Video PLL divider fix - i.MX6UL/ULL epdc_podf support - Hi3798CV200 COMBPHY0 and USB2_OTG_UTMI and phase support for eMMC -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAlrPhMARHHNib3lkQGtl cm5lbC5vcmcACgkQrQKIl8bklSVkkxAArsItSoxQV18kQlJ9S7o2z75giquXQfvy Y/cKIIY1kz4K+qm+rpbl6PjukrSPtfM+wGmepGt+CptOdlj672viFxI7zjrd1iSy /xJo7d5/nZxvmx0qcwYWVTCOsU+4FUUkpq5mE91KEvwny/qgRqEgWeLoWTDLBktF MzGtBUYudjkRYLd2I31DGB3dqI0Dy9JwuEpJfCAt5h4dztml3aNjYknjQ/vUSEXL 61mSYM1fwzK8rnrjSlQqb+X0OoJ6d5Pz2uHRXnWfGlS8UOh5N9NFGKpiErLm+h/+ /FigA6f9HBeUneNf5Dnu568FHwE2FyUbZKVd40OYj3x128OnAoKUoRt68/8FQPdf NoQb3zH3Ha1JbwWgvQ9RkWp82kYnMctrlkh6IFye/FxdfwCWA4SE/iIgJXRJbQ/K blZz14jkXT8oISqy6nryGv3CK/RFXzVdvVa4z41xHc4cnLpNBsv1o89a+9MyTvMD wYOnc/98/l5xYs5PvQqNrd/onE0GLIeOEtkWNXH0OACe6FOIuz5eVn4Uh8aIm0wl +EHwHRwB7AQK+a7jwEfQ88aceAntvFlymUUcsncyCXn2s0knc5BHJPSHhoZk1tJb Wv2Fcln3Mwjhhq9aoNxfAJf4pIqmFgdQEtwyND4GJlP55Xay5QMZVEdwnNfFDvmf X6P2pfkBqkg= =ys4O -----END PGP SIGNATURE----- Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "The large diff this time around is from the addition of a new clk driver for the TI Davinci family of SoCs. So far those clks have been supported with a custom implementation of the clk API in the arch port instead of in the CCF. With this driver merged we're one step closer to having a single clk API implementation. The other large diff is from the Amlogic clk driver that underwent some major surgery to use regmap. Beyond that, the biggest hitter is Samsung which needed some reworks to properly handle clk provider power domains and a bunch of PLL rate updates. The core framework was fairly quiet this round, just getting some cleanups and small fixes for some of the more esoteric features. And the usual set of driver non-critical fixes, cleanups, and minor additions are here as well. Core: - Rejig clk_ops::init() to be a little earlier for phase/accuracy ops - debugfs ops macroized to shave some lines of boilerplate code - Always calculate the phase instead of caching it in clk_get_phase() - More __must_check on bulk clk APIs New Drivers: - TI's Davinci family of SoCs - Intel's Stratix10 SoC - stm32mp157 SoC - Allwinner H6 CCU - Silicon Labs SI544 clock generator chip - Renesas R-Car M3-N and V3H SoCs - i.MX6SLL SoCs Removed Drivers: - ST-Ericsson AB8540/9540 Updates: - Mediatek MT2701 and MT7622 audsys support and MT2712 updates - STM32F469 DSI and STM32F769 sdmmc2 support - GPIO clks can sleep now - Spreadtrum SC9860 RTC clks - Nvidia Tegra MBIST workarounds and various minor fixes - Rockchip phase handling fixes and a memory leak plugged - Renesas drivers switch to readl/writel from clk_readl/clk_writel - Renesas gained CPU (Z/Z2) and watchdog support - Rockchip rk3328 display clks and rk3399 1.6GHz PLL support - Qualcomm PM8921 PMIC XO buffers - Amlogic migrates to regmap APIs - TI Keystone clk latching support - Allwinner H3 and H5 video clk fixes - Broadcom BCM2835 PLLs needed another bit to enable - i.MX6SX CKO mux fix and i.MX7D Video PLL divider fix - i.MX6UL/ULL epdc_podf support - Hi3798CV200 COMBPHY0 and USB2_OTG_UTMI and phase support for eMMC" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (233 commits) clk: davinci: add a reset lookup table for psc0 clk: imx: add clock driver for imx6sll dt-bindings: imx: update clock doc for imx6sll clk: imx: add new gate/gate2 wrapper funtion clk: imx: Add CLK_IS_CRITICAL flag for busy divider and busy mux clk: cs2000: set pm_ops in hibernate-compatible way clk: bcm2835: De-assert/assert PLL reset signal when appropriate clk: imx7d: Move clks_init_on before any clock operations clk: imx7d: Correct ahb clk parent select clk: imx7d: Correct dram pll type clk: imx7d: Add USB clock information clk: socfpga: stratix10: add clock driver for Stratix10 platform dt-bindings: documentation: add clock bindings information for Stratix10 clk: ti: fix flag space conflict with clkctrl clocks clk: uniphier: add additional ethernet clock lines for Pro4 clk: uniphier: add SATA clock control support clk: uniphier: add PCIe clock control support clk: Add driver for the si544 clock generator chip clk: davinci: Remove redundant dev_err calls clk: uniphier: add ethernet clock control support for PXs3 ... |
||
|
Linus Torvalds
|
38c23685b2 |
ARM: SoC driver updates for 4.17
The main addition this time around is the new ARM "SCMI" framework,
which is the latest in a series of standards coming from ARM to do power
management in a platform independent way. This has been through many
review cycles, and it relies on a rather interesting way of using the
mailbox subsystem, but in the end I agreed that Sudeep's version was
the best we could do after all.
Other changes include:
- the ARM CCN driver is moved out of drivers/bus into drivers/perf,
which makes more sense. Similarly, the performance monitoring
portion of the CCI driver are moved the same way and cleaned up
a little more.
- a series of updates to the SCPI framework
- support for the Mediatek mt7623a SoC in drivers/soc
- support for additional NVIDIA Tegra hardware in drivers/soc
- a new reset driver for Socionext Uniphier
- lesser bug fixes in drivers/soc, drivers/tee, drivers/memory, and
drivers/firmware and drivers/reset across platforms
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Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver updates from Arnd Bergmann:
"The main addition this time around is the new ARM "SCMI" framework,
which is the latest in a series of standards coming from ARM to do
power management in a platform independent way.
This has been through many review cycles, and it relies on a rather
interesting way of using the mailbox subsystem, but in the end I
agreed that Sudeep's version was the best we could do after all.
Other changes include:
- the ARM CCN driver is moved out of drivers/bus into drivers/perf,
which makes more sense. Similarly, the performance monitoring
portion of the CCI driver are moved the same way and cleaned up a
little more.
- a series of updates to the SCPI framework
- support for the Mediatek mt7623a SoC in drivers/soc
- support for additional NVIDIA Tegra hardware in drivers/soc
- a new reset driver for Socionext Uniphier
- lesser bug fixes in drivers/soc, drivers/tee, drivers/memory, and
drivers/firmware and drivers/reset across platforms"
* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (87 commits)
reset: uniphier: add ethernet reset control support for PXs3
reset: stm32mp1: Enable stm32mp1 reset driver
dt-bindings: reset: add STM32MP1 resets
reset: uniphier: add Pro4/Pro5/PXs2 audio systems reset control
reset: imx7: add 'depends on HAS_IOMEM' to fix unmet dependency
reset: modify the way reset lookup works for board files
reset: add support for non-DT systems
clk: scmi: use devm_of_clk_add_hw_provider() API and drop scmi_clocks_remove
firmware: arm_scmi: prevent accessing rate_discrete uninitialized
hwmon: (scmi) return -EINVAL when sensor information is unavailable
amlogic: meson-gx-socinfo: Update soc ids
soc/tegra: pmc: Use the new reset APIs to manage reset controllers
soc: mediatek: update power domain data of MT2712
dt-bindings: soc: update MT2712 power dt-bindings
cpufreq: scmi: add thermal dependency
soc: mediatek: fix the mistaken pointer accessed when subdomains are added
soc: mediatek: add SCPSYS power domain driver for MediaTek MT7623A SoC
soc: mediatek: avoid hardcoded value with bus_prot_mask
dt-bindings: soc: add header files required for MT7623A SCPSYS dt-binding
dt-bindings: soc: add SCPSYS binding for MT7623 and MT7623A SoC
...
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||
|
Gabriel Fernandez
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dae5af9762 |
dt-bindings: reset: add STM32MP1 resets
This patch adds the reset binding entry for STM32MP1 Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> |
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Icenowy Zheng
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524353ea48
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clk: sunxi-ng: add support for the Allwinner H6 CCU
The Allwinner H6 SoC has a CCU which has been largely rearranged. Add support for it in the sunxi-ng CCU framework. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> |