3 Commits

Author	SHA1	Message	Date
Dmitry Baryshkov	f9d35dd39b	phy: qualcomm: qmp-pcie: split PCS_LANE1 region ... The PCS_LANE1 region isn't a part of the PCS_PCIE region. It was handled this way as it simplified handled of devices with the old bindings. Nowadays it can be handled as is, without hacks. Split the PCS_LANE1 region from the PCS_PCIE / PCS_MISC region space. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20241021-sar2130p-phys-v2-4-d883acf170f7@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>	2024-12-08 21:30:08 +05:30
Manivannan Sadhasivam	364c748d5e	phy: qcom-qmp-pcie: Add RC init sequence for SDX55 ... Add PCIe RC init sequence making use of the common init sequence. The RC mode additionally requires REFCLK_DRV_DSBL bit to set during powerup and powerdown. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20230308082424.140224-13-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>	2023-03-20 18:14:55 +05:30
Dmitry Baryshkov	25ad4a4cfe	phy: qcom-qmp: split allegedly 4.20 and 5.20 PCS registers ... Split registers definitions belonging allegedly to 4.20 and 5.20 QMP PHYs. They are used for the PCIe QMP PHYs, which have no good open source reference. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220705094320.1313312-20-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>	2022-07-07 10:36:00 +05:30