Commit Graph

21 Commits

Author SHA1 Message Date
Jai Luthra
cd403e8aed media: rockchip: rkisp1: Add support for Wide Dynamic Range
RKISP supports a basic Wide Dynamic Range (WDR) module since the first
iteration (v1.0) of the ISP. Add support for enabling and configuring it
using extensible parameters.

Also, to ease programming, switch to using macro variables for defining
the tonemapping curve register addresses.

Reviewed-by: Stefan Klug <stefan.klug@ideasonboard.com>
Tested-by: Stefan Klug <stefan.klug@ideasonboard.com>
Reviewed-by: Paul Elder <paul.elder@ideasonboard.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Jai Luthra <jai.luthra@ideasonboard.com>
Link: https://lore.kernel.org/r/20250610-wdr-latest-v4-1-b69d0ac17ce9@ideasonboard.com
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-06-18 09:21:58 +02:00
Stefan Klug
2e79181dfc media: rkisp1: Remove unnecessary defines
The effect modes are not shifts but numbers which are already defined a
few lines above. Remove the misleading defines.

Signed-off-by: Stefan Klug <stefan.klug@ideasonboard.com>
Link: https://lore.kernel.org/r/20250227114558.3097101-4-stefan.klug@ideasonboard.com
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2025-05-01 14:07:01 +02:00
Paul Elder
a735e53975 media: rkisp1: Add register definitions for the companding block
To prepare for adding support for the companding block to the rkisp1
driver for the version of the ISP on the i.MX8MP, add the register
definitions for it, including relevant register field values.

Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
Reviewed-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com>
Signed-off-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com>
Tested-by: Kieran Bingham <kieran.bingham@ideasonboard.com>
Acked-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2024-08-14 16:42:57 +03:00
Paul Elder
6c144351f2 media: rkisp1: Fix endianness on raw streams on i.MX8MP
The i.MX8MP has extra register fields in the memory interface control
register for setting the output format, which work with the output
alignment format register for byte-swapping and LSB/MSB alignment.

With processed and 8-bit raw streams, it doesn't cause any problems to
not set these, but with raw streams of higher bit depth the endianness
is swapped and the data is not aligned properly.

Add support for setting these registers and plumb them in to fix this.

While at it, reflow a comment related to the forced configuration
update.

Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
2024-02-23 14:23:32 +02:00
Paul Elder
bcb40cc113 media: rkisp1: Support setting memory stride for main path
Some versions of the ISP supported by the rkisp1 driver, such as the ISP
in the i.MX8MP, implement configurable memory stride for the main path
the same way as already implemented by the driver for the self path.
Support this feature by adding a main stride feature flag and program
the corresponding registers accordingly.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Tested-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
2024-02-23 14:23:17 +02:00
Paul Elder
02f2c7b457 media: rkisp1: regs: Consolidate MI interrupt wrap fields
Consolidate the wraparound fields in the memory interface interrupt
status registers, so that it can be more succinctly expressed by taking
the stream ID (main or self) as a parameter.

Link: https://lore.kernel.org/r/20231201140433.2126011-2-paul.elder@ideasonboard.com

Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
Reviewed-by: Kieran Bingham <kieran.bingham@ideasonboard.com>
Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
2023-12-09 07:45:53 +01:00
Laurent Pinchart
cde4e5157a media: rkisp1: Convert hex constants to lowercase
Hex constants in the media subsystem are typically in lowercase. The
rkisp1 driver mostly follows that convention already, except in the
register definitions. Convert all hex constants to lowercase for
consistency.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
2023-10-12 09:46:37 +02:00
Laurent Pinchart
4c3501f13e media: rkisp1: Use correct macro for gradient registers
The rkisp1_lsc_config() function incorrectly uses the
RKISP1_CIF_ISP_LSC_SECT_SIZE() macro for the gradient registers. Replace
it with the correct macro, and rename it from
RKISP1_CIF_ISP_LSC_GRAD_SIZE() to RKISP1_CIF_ISP_LSC_SECT_GRAD() as the
corresponding registers store the gradients for each sector, not a size.
This doesn't cause any functional change as the two macros are defined
identically (the size and gradient registers store fields in the same
number of bits at the same positions).

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Dafna Hirschfeld <dafna@fastmail.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
2022-09-24 08:41:31 +02:00
Laurent Pinchart
10e36b2191 media: rkisp1: Simplify LSC x/y size and grad register macros
The LSC module x/y size and grad configuration is stored in a set of 4
indexed registers each. The rkisp1-regs.h header defines all those
registers, but only the first one in each set is used, with manual
calculation of addresses of subsequent registers. Simplifies this by
merging all 4 register macros into one that takes the index as a
parameter. No functional change intended.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Dafna Hirschfeld <dafna@fastmail.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
2022-09-24 08:41:01 +02:00
Laurent Pinchart
8e2b7442d2 media: rockchip: rkisp1: Define macros for DPCC configurations in UAPI
Extend the UAPI rkisp1-config.h header with macros for all DPCC
configuration fields. While at it, clarify of fix issues in the DPCC
documentation.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Paul Elder <paul.elder@ideasonboard.com>
Reviewed-by: Dafna Hirschfeld <dafna@fastmail.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
2022-09-24 08:31:54 +02:00
Laurent Pinchart
9daa2b843f media: rockchip: rkisp1: Mask invalid bits in DPCC parameters
Restrict the DPCC configuration that can be set by userspace to valid
register bits. To do so, reorganize the related register macros to
define valid bitmasks, as well as bits of the DPCC mode register.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Paul Elder <paul.elder@ideasonboard.com>
Reviewed-by: Dafna Hirschfeld <dafna@fastmail.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
2022-09-24 07:54:04 +02:00
Laurent Pinchart
cbb819c363 media: rkisp1: debug: Collect input status by sampling ISP_FLAGS_SHD
The ISP_FLAGS_SHD register exposes the ISP parallel input signals (data
and synchronization) in real time. This can help debugging when the
device doesn't output any image. Sample the register 10000 times with a
1µs delay and expose the result through debugfs.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
Reviewed-by: Ricardo Ribalda <ribalda@chromium.org>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
2022-06-27 08:36:32 +01:00
Laurent Pinchart
3e74a42223 media: rkisp1: resizer: Simplify register access
The registers for the mainpath and selfpath resizers are located at the
same offset from the instance-specific base. Use this to simplify
register access, removing the need to store per-register offsets in the
rkisp1_rsz_config structure.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Ricardo Ribalda <ribalda@chromium.org>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
2022-06-27 08:33:33 +01:00
Laurent Pinchart
3b430c2cf0 media: rkisp1: regs: Rename CCL, ICCL and IRCL registers with VI_ prefix
The documentation names the CCL, ICCL and IRCL registers with a VI_
prefix, like the VI_ID and VI_DPCL registers. Fix the macro names
accordingly.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Dafna Hirschfeld <dafna@fastmail.com>
Reviewed-by: Ricardo Ribalda <ribalda@chromium.org>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
2022-06-27 08:05:21 +01:00
Laurent Pinchart
240e92eaee media: rkisp1: regs: Don't use BIT() macro for multi-bit register fields
The BIT() macro is meant to represent a single bit. It is incorrectly
used for register field values that store the value 1 in a multi-bit
field. Use the usual (1 << n) construct for those.

While at it, move RKISP1_CIF_MI_DMA_CTRL_READ_FMT_PACKED where it
belongs with the other READ_FMT values.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Ricardo Ribalda <ribalda@chromium.org>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
2022-06-27 08:04:08 +01:00
Laurent Pinchart
117368f0c4 media: rockchip: rkisp1: Use mipi-csi2.h
Replace the driver-specific definitions of MIPI CSI-2 data types with
macros from mipi-csi2.h.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Dafna Hirschfeld <dafna.hirschfeld@collabora.com>
Reviewed-by: Dafna Hirschfeld <dafna.hirschfeld@collabora.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
2022-05-13 11:02:20 +02:00
Heiko Stuebner
cd42f8023f media: rockchip: rkisp1: add support for v12 isp variants
The rkisp1 evolved over soc generations and the rk3326/px30 introduced
the so called v12 - probably meaning v1.2.

Add the new register definitions.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Dafna Hirschfeld <dafna.hirschfeld@collabora.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2021-09-30 10:07:37 +02:00
Heiko Stuebner
dce8ccb232 media: rockchip: rkisp1: add prefixes for v10 specific parts
The rkisp1 evolved over soc generations and the rk3326/px30 introduced
the so called v12 - probably meaning v1.2.

In a first step adapt the affected v10 parts to give them a
matching suffix to enable us to add v12 variants later on.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Dafna Hirschfeld <dafna.hirschfeld@collabora.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2021-09-30 10:07:37 +02:00
Dafna Hirschfeld
a802a0430b media: rkisp1: stats: mask the hist_bins values
hist_bins is an array of type __u32. Each entry represents
a 20 bit value. So mask out the unused bits.

Signed-off-by: Dafna Hirschfeld <dafna.hirschfeld@collabora.com>
Acked-by: Helen Koike <helen.koike@collabora.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2021-01-28 11:30:04 +01:00
Peilin Ye
6b94c09f82 media: rockchip: rkisp1: Fix typos in comments and macro definitions
Fix 4 typos under drivers/media/platform/rockchip/rkisp1/ found by
checkpatch, including the RKISP1_CIF_MI_{M,S}P_PINGPONG_ENABLE macro
definitions.

Signed-off-by: Peilin Ye <yepeilin.cs@gmail.com>
Acked-by: Helen Koike <helen.koike@collabora.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-03 08:23:13 +01:00
Helen Koike
e6938cc1cb media: rockchip: rkisp1: destage Rockchip ISP1 driver
All the items in the TODO list were addressed, uapi was reviewed,
documentation written, checkpatch errors fixed, several bugs fixed.

There is no big reason to keep this driver in staging, so move it out.

Dt-bindings Verified with:
make ARCH=arm64 dt_binding_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/media/rockchip-isp1.yaml

Fields of MAINTAINERS file sorted according to output of
./scripts/parse-maintainers.pl --input=MAINTAINERS --output=MAINTAINERS
--order

[dt-bindings: media: rkisp1: move rockchip-isp1 bindings out of staging]
[dt-bindings: media: rkisp1: move rockchip-isp1 bindings out of staging]
[hverkuil: fix various checkpatch alignment warnings]

Signed-off-by: Helen Koike <helen.koike@collabora.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Tomasz Figa <tfiga@chromium.org>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-11-17 07:01:17 +01:00