Commit Graph

4 Commits

Author SHA1 Message Date
Amit Vadhavana
a688efea0f dmaengine: Fix spelling mistakes
Correct spelling mistakes in the DMA engine to improve readability
and clarity without altering functionality.

Signed-off-by: Amit Vadhavana <av2082000@gmail.com>
Reviewed-by: Kees Cook <kees@kernel.org>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Fenghua Yu <fenghua.yu@intel.com>
Link: https://lore.kernel.org/r/20240831172949.13189-1-av2082000@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-09-02 13:56:01 +05:30
Frank Li
bd2f66bc0b dmaengine: fsl-dpaa2-qdma: Update DPDMAI interfaces to version 3
Update the DPDMAI interfaces to support MC firmware up to 10.1x.x, which
major change is to add dpaa domain id support. User space MC controller
tool can create difference dpaa domain for difference virtual environment.
DMA queues can map to difference service priorities.

The MC command was basic compatible original one. The new command use
previous reserved field.

- Add queue number for dpdmai_get_tx(rx)_queue().
- Unified rx(tx)_queue_attr.
- Update pad/reserved field of struct dpdmai_rsp_get_attributes and
struct dpdmai_cmd_queue for new API.
- Update command DPDMAI_SET(GET)_RX_QUEUE and DPDMAI_CMDID_GET_TX_QUEUE

Signed-off-by: Frank Li <Frank.Li@nxp.com>
Link: https://lore.kernel.org/r/20240409163630.1996052-1-Frank.Li@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-04-17 22:42:38 +05:30
Geert Uytterhoeven
a0754cf3b3 dmaengine: fsl-dpaa2-qdma: Drop comma after SoC match table sentinel
It does not make sense to have a comma after a sentinel, as any new
elements must be added before the sentinel.

Add a comment to clarify the purpose of the empty element.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/0b8ad4dcc185aa7a17655983e0eb5690d8fed460.1646311558.git.geert+renesas@glider.be
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-03-11 15:47:39 +05:30
Peng Ma
7fdf9b05c7 dmaengine: fsl-dpaa2-qdma: Add NXP dpaa2 qDMA controller driver for Layerscape SoCs
DPPA2(Data Path Acceleration Architecture 2) qDMA supports
virtualized channel by allowing DMA jobs to be enqueued into
different work queues. Core can initiate a DMA transaction by
preparing a frame descriptor(FD) for each DMA job and enqueuing
this job through a hardware portal. DPAA2 components can also
prepare a FD and enqueue a DMA job through a hardware portal.
The qDMA prefetches DMA jobs through DPAA2 hardware portal. It
then schedules and dispatches to internal DMA hardware engines,
which generate read and write requests. Both qDMA source data and
destination data can be either contiguous or non-contiguous using
one or more scatter/gather tables.
The qDMA supports global bandwidth flow control where all DMA
transactions are stalled if the bandwidth threshold has been reached.
Also supported are transaction based read throttling.

Add NXP dppa2 qDMA to support some of Layerscape SoCs.
such as: LS1088A, LS208xA, LX2, etc.

Signed-off-by: Peng Ma <peng.ma@nxp.com>
Link: https://lore.kernel.org/r/20190930020440.7754-2-peng.ma@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2019-10-17 09:41:07 +05:30