device_get_match_data() function should not be used on the device other
than the one matched to the given driver, because it always returns the
match_data of the matched driver. In case of exynos-clkout driver, the
original code matches the OF IDs on the PARENT device, so replacing it
with of_device_get_match_data() broke the driver.
This has been already pointed once in commit 2bc5febd05 ("clk: samsung:
Revert "clk: samsung: exynos-clkout: Use of_device_get_match_data()"").
To avoid further confusion, add a comment about this special case, which
requires direct of_match_device() call to pass custom IDs array.
This partially reverts commit 409c39ec92.
Cc: <stable@vger.kernel.org>
Fixes: 409c39ec92 ("clk: Use device_get_match_data()")
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Link: https://lore.kernel.org/r/20240425075628.838497-1-m.szyprowski@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240430184656.357805-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
CMU_HSI2 is the clock management unit used for the hsi2 block.
HSI stands for High Speed Interface and as such it generates
clocks for PCIe, UFS and MMC card.
This patch adds support for the muxes, dividers, and gates in
cmu_hsi2.
The following clocks are marked CLK_IS_CRITICAL as disabling
them results in an immediate system hang.
CLK_GOUT_HSI2_HSI2_CMU_HSI2_PCLK
CLK_GOUT_HSI2_LHM_AXI_P_HSI2_I_CLK
The following clocks are marked CLK_IGNORE_UNUSED as they are
needed for UFS to be functional.
CLK_GOUT_HSI2_SSMT_HSI2_ACLK
CLK_GOUT_HSI2_SSMT_HSI2_PCLK
CLK_GOUT_HSI2_LHS_ACEL_D_HSI2_I_CLK
CLK_GOUT_HSI2_SYSMMU_HSI2_CLK_S2
CLK_GOUT_HSI2_XIU_D_HSI2_ACLK
CLK_GOUT_HSI2_XIU_P_HSI2_ACLK
CLK_GOUT_HSI2_GPIO_HSI2_PCLK is marked CLK_IGNORE_UNUSED until
the exynos pinctrl clock patches land then it can be removed.
Some clocks in this unit have very long names. To help with this
the clock name mangling strategy was updated to include removing
the following sub-strings.
- G4X2_DWC_PCIE_CTL_
- G4X1_DWC_PCIE_CTL_
- PCIE_SUB_CTRL_
- INST_0_
- LN05LPE_
- TM_WRAPPER_
- SF_
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
[AD: resolve merge conflicts]
Signed-off-by: André Draszik <andre.draszik@linaro.org>
Reviewed-by: André Draszik <andre.draszik@linaro.org>
Link: https://lore.kernel.org/r/20240429-hsi0-gs101-v3-3-f233be0a2455@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
CMU_HSI0 is the clock management unit for one of the high speed
interfaces, which is used (amongst others) for USB
Some notes about the clocks marked as CLK_IGNORE_UNUSED:
* CLK_GOUT_HSI0_PCLK
CLK_GOUT_HSI0_LHM_AXI_P_HSI0_I_CLK
CLK_GOUT_HSI0_XIU_P_HSI0_ACLK need to be kept running as
otherwise the system becomes unresponsive and it doesn't complete
booting.
* CLK_GOUT_HSI0_LHS_ACEL_D_HSI0_I_CLK
CLK_GOUT_HSI0_SSMT_USB_ACLK
CLK_GOUT_HSI0_SSMT_USB_PCLK
CLK_GOUT_HSI0_SYSMMU_USB_CLK_S2
CLK_GOUT_HSI0_XIU_D0_HSI0_ACLK
CLK_GOUT_HSI0_XIU_D1_HSI0_ACLK are needed for USB to come up
properly (SSMT is for (secure) memory tagging).
While at the moment we only support booting with the clk_ignore_unused
kernel command line paramenter, it's still worthwhile to explicitly
mark those clocks.
While the usual (sed) script has been used to derive the linux clock
names from the data sheet, one manual tweak was applied to fix a typo
coming from the data sheet which we don't want to carry:
hsi0_uspdpdbg_user -> hsi0_usbdpdbg_user (note usb vs usp).
Signed-off-by: André Draszik <andre.draszik@linaro.org>
Link: https://lore.kernel.org/r/20240426-hsi0-gs101-v2-4-2157da8b63e3@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
When SPI transfer is being prepared, the spi-s3c64xx driver will call
clk_set_rate() to change the rate of SPI source clock (IPCLK). But IPCLK
is a gate (leaf) clock, so it must propagate the rate change up the
clock tree, so that corresponding MUX/DIV clocks can actually change
their values. Add CLK_SET_RATE_PARENT flag to corresponding clocks for
all USI instances in GS101 PERIC1: USI{0, 9, 10, 11, 12, 13}. This change
involves the following clocks:
PERIC1 USI*:
Clock Div range MUX Selection
-------------------------------------------------------------------
gout_peric1_peric1_top0_ipclk_* - -
dout_peric1_usi*_usi /1..16 -
mout_peric1_usi*_usi_user - {24.5 MHz, 400 MHz}
With input clock of 400 MHz this scheme provides the following IPCLK
rate range, for each USI block:
PERIC1 USI*: 1.5 MHz ... 400 MHz
Accounting for internal /4 divider in SPI blocks, and because the max
SPI frequency is limited at 50 MHz, it gives us next SPI SCK rates:
PERIC1 USI_SPI*: 384 KHz ... 49.9 MHz
Which shall be fine for the applications of the SPI bus.
Note that with this we allow the reparenting of the MUX_USIx clocks to
OSCCLK. Each instance of the USI IP has its own MUX_USI clock, thus the
reparenting of a MUX_USI clock corresponds to a single instance of the
USI IP. The datasheet mentions OSCCLK just in the low-power mode
context, but the downstream driver reparents too the MUX_USI clocks to
OSCCLK. Follow the downstream driver and do the same.
Fixes: 2999e786d7 ("clk: samsung: gs101: add support for cmu_peric1")
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Acked-by: André Draszik <andre.draszik@linaro.org>
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Link: https://lore.kernel.org/r/20240419100915.2168573-3-tudor.ambarus@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Introduce nMUX() for MUX clocks that can be reparented on clock rate
change. "nMUX" comes from "n-to-1 selector", hopefully emphasising that
the selector can change on clock rate changes. Ideally MUX/MUX_F()
should change to not have the CLK_SET_RATE_NO_REPARENT flag set by
default, and all their users to be updated to add the flag back
(like in the case of DIV and GATE). But this is a very intrusive change
and because for now only GS101 allows MUX reparenting on clock rate
change, stick with nMUX().
GS101 defines MUX clocks that are dedicated for each instance of the IP.
One example is USI IP (SPI, I2C, serial). The reparenting of these MUX
clocks will not affect other instances of the same IP or different IPs
altogether.
When SPI transfer is being prepared, the spi-s3c64xx driver will call
clk_set_rate() to change the rate of SPI source clock (IPCLK). But IPCLK
is a gate (leaf) clock, so it must propagate the rate change up the
clock tree, so that corresponding MUX/DIV clocks can actually change
their values. Add CLK_SET_RATE_PARENT flag to corresponding clocks for
all USI instances in GS101 PERIC0: USI{1-8, 14}. This change involves the
following clocks:
PERIC0 USI*:
Clock Div range MUX Selection
-------------------------------------------------------------------
gout_peric0_peric0_top0_ipclk_* - -
dout_peric0_usi*_usi /1..16 -
mout_peric0_usi*_usi_user - {24.5 MHz, 400 MHz}
With input clock of 400 MHz this scheme provides the following IPCLK
rate range, for each USI block:
PERIC0 USI*: 1.5 MHz ... 400 MHz
Accounting for internal /4 divider in SPI blocks, and because the max
SPI frequency is limited at 50 MHz, it gives us next SPI SCK rates:
PERIC0 USI_SPI*: 384 KHz ... 49.9 MHz
Fixes: 893f133a04 ("clk: samsung: gs101: add support for cmu_peric0")
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Acked-by: André Draszik <andre.draszik@linaro.org>
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Link: https://lore.kernel.org/r/20240419100915.2168573-2-tudor.ambarus@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
All PLL id values of CMU_TOP were incorrectly set to FOUT_SHARED0_PLL.
It modified to the correct PLL clock id value.
Fixes: 6587c62f69 ("clk: samsung: add top clock support for Exynos Auto v9 SoC")
Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20240328091000.17660-1-jaewon02.kim@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Implement support for CPU clock management units:
- CMU_CPUCL0: clocks for cluster 0: 4 x Cortex-A55 (cpu0..cpu3)
- CMU_CPUCL1: clocks for cluster 1: 4 x Cortex-A55 (cpu4..cpu7)
CPU PLLs are generating main CPU clocks for each cluster, and there are
alternate ("switch") clocks that can be used temporarily while
re-configuring the PLL for a new rate. ACLK, ATCLK, PCLKDBG and
PERIPHCLK clocks are driving corresponding buses. CLK_CLUSTERx_SCLK are
actual leaf CPU clocks and should be used to change CPU rates. Also some
CoreSight clocks can be derived from DBG_USER (debug clock).
PLL table was extracted from ECT table. ECT stands for "Exynos
Characteristic Table", it's a Samsung specific binary data populated by
BL2 bootloader in RAM at 0x90000000 address, containing PLL tables for
various CMUs and other hardware specific information.
The particular PLL type used in CMU_CPUCL0 and CMU_CPUCL1 (pll0822x) is
an integer PLL with middle FVCO. The equation to calculate its output
rate is:
fout = fin * M / (P*2^S)
where:
fin = 26 MHz (OSCCLK frequency)
M = 64..1023
P = 1..63
S = 0..6
The PLL table tries to keep "P" value low to reduce the locking time,
which for pll0822x is "t = P * 150" (in OSCCLK cycles).
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20240301015118.30072-2-semen.protsenko@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Some ARM64 Exynos chips are capable to control PLL clocks automatically.
For those chips, whether the PLL is controlled automatically or manually
is chosen in PLL_CON1 register with next bits:
[28] ENABLE_AUTOMATIC_CLKGATING
[1] MANUAL_PLL_CTRL
[0] AUTO_PLL_CTRL
The bl2 bootloader sets 0x10000001 value for some PLL_CON1 registers,
which means any attempt to control those PLLs manually (e.g.
disabling/enabling those PLLs or changing MUX parent clocks) would lead
to PLL lock timeout with error message like this:
Could not lock PLL ...
At the moment, all Samsung clock drivers implement manual clock control.
So in order to make it possible to control PLLs, corresponding PLL_CON1
registers should be set to 0x2 first.
Some older ARM64 chips don't implement the automatic clock control
though. It also might be desirable to configure some PLLs for manual
control, while keeping the default configuration for the rest. So it'd
convenient to choose this PLL mode for each CMU separately. Introduce
.manual_plls field to CMU structure to choose the PLL control mode.
Because it'll be initialized with "false" in all existing CMU
structures by default, it won't affect any existing clock drivers,
allowing for this feature to be enabled gradually when it's needed with
no change for the rest of users. In case .manual_plls is set, set
PLL_CON1 registers to manual control, akin to what's already done for
gate clocks in exynos_arm64_init_clocks(). Of course, PLL_CON1 registers
should be added to corresponding struct samsung_cmu_info::clk_regs array
to make sure they get initialized.
No functional change. This patch adds a feature, but doesn't enable it
for any users.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20240301015118.30072-1-semen.protsenko@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Implement CPU clock control for Exynos850 SoC. It follows the same
procedure which is already implemented for other SoCs in clk-cpu.c:
1. Set the correct rate for the alternate parent (if needed) before
switching to use it as the CPU clock
2. Switch to the alternate parent, so the CPU continues to get clocked
while the PLL is being re-configured
3. Adjust the dividers for the CPU related buses (ACLK, ATCLK, etc)
4. Re-configure the PLL for the new CPU clock rate. It's done
automatically, as the CPU clock rate change propagates to the PLL
clock, because the CPU clock has CLK_SET_RATE_PARENT flag set in
exynos_register_cpu_clock()
5. Once the PLL is locked, set it back as the CPU clock source
6. Set alternate parent clock rate back to max speed
As in already existing clk-cpu.c code, the divider and mux clocks are
configured in a low-level fashion (using direct register access instead
of CCF API), to avoid affecting how DIV and MUX clock flags are declared
in the actual clock driver (clk-exynos850.c).
No functional change. This patch adds support for Exynos850 CPU clock,
but doesn't enable it per se.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20240224202053.25313-13-semen.protsenko@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Make it possible to use wait_until_mux_stable() for MUX registers where
the mask is different from MUX_MASK (e.g. in upcoming CPU clock
implementation for Exynos850).
No functional change.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20240224202053.25313-12-semen.protsenko@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Abstract CPU clock registers by keeping their offsets in a dedicated
chip specific structure to accommodate for oncoming Exynos850 support,
which has different offsets for cluster 0 and cluster 1. This rework
also makes it possible to use exynos_set_safe_div() for all chips, so
exynos5433_set_safe_div() is removed here to reduce the code
duplication. The ".regs" field has to be (void *) as different Exynos
chips can have very different register layout, so this way it's possible
for ".regs" to point to different structures, each representing its own
chip's layout.
No functional change.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20240224202053.25313-11-semen.protsenko@linaro.org
[krzysztof: drop redundant const for regs in exynos_cpuclk_chip]
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Keep chip specific data in the data structure, don't mix it with code.
It makes it easier to add more chip specific data further. Having all
chip specific data in the table eliminates possible code bloat when
adding more rate handlers for new chips, and also makes it possible to
keep some other chip related data in that array.
No functional change.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20240224202053.25313-10-semen.protsenko@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Use a dedicated enum field to explicitly specify which register layout
should be used for the CPU clock, instead of passing it as a bit flag.
This way it would be possible to keep the chip-specific data in some
array, where each chip structure could be accessed by its corresponding
layout index. It prepares clk-cpu.c for adding new chips support, which
might have different data for different CPU clusters.
No functional change.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20240224202053.25313-9-semen.protsenko@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
The documentation for struct exynos_cpuclk says .ctrl_base field should
contain the controller base address. There are two different problems
with that:
1. All Exynos clock drivers are actually passing CPU_SRC register offset
via CPU_CLK() macro, which in turn gets assigned to mentioned
.ctrl_base field. Because CPU_SRC register usually already has 0x200
offset from controller's base, all other register offsets in
clk-cpu.c (like DIVs and MUXes) are specified as offsets from CPU_SRC
offset, and not from controller's base. That makes things confusing
and inconsistent with register offsets provided in Exynos clock
drivers, also breaking the contract for .ctrl_base field as described
in struct exynos_cpuclk doc.
2. Furthermore, some Exynos chips have an additional offset for the
start of CPU clock registers block (inside of the CMU). There might
be different reasons for that, e.g.:
- The CMU contains clocks for two different CPUs (like in Exynos5420)
- The CMU contains also non-CPU clocks as well (like in Exynos4)
- The CPU CMU exists as a dedicated hardware block in the SoC layout,
but is modelled as a part of bigger CMU in the driver (like in case
of Exynos3250)
That means the .ctrl_base field is actually not a controller's base,
but instead it's a start address of the CPU clock registers inside of
the CMU.
Rework all register offsets in clk-cpu.c to be actual offsets from the
CPU clock register block start, and fix offsets provided to CPU_CLK()
macro in all Exynos clock drivers. Also clarify the .ctrl_base field
documentation and rename it to just .base, because it doesn't really
contain the CMU base.
No functional change.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20240224202053.25313-8-semen.protsenko@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
clk-cpu.c is going to get messy as new chips support is added.
Restructure the code by pulling related functions and definitions
together, grouping those by their relation to a particular chip or other
categories, to simplify the code navigation.
No functional change.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20240224202053.25313-7-semen.protsenko@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reduce the code duplication by making all chips use a single version of
exynos_cpuclk_notifier_cb() function. That will prevent the code bloat
when adding new chips support too.
Also don't pass base address to pre/post rate change functions, as it
can be easily derived from already passed cpuclk param.
No functional change.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20240224202053.25313-6-semen.protsenko@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Pass CPU clock data structure to exynos_register_cpu_clock() instead of
passing its fields separately there. That simplifies the signature of
exynos_register_cpu_clock() and makes it easier to add more fields to
struct samsung_cpu_clock later. This style follows the example of
samsung_clk_register_pll().
No functional change.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20240224202053.25313-5-semen.protsenko@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reduce the scope of struct exynos_cpuclk, as it's only used in clk-cpu.c
internally. All drivers using clk-pll.h already include clk.h as well,
so this change doesn't break anything.
No functional change.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20240224202053.25313-4-semen.protsenko@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
clk-cpu.c has numerous style issues reported by checkpatch and easily
identified otherwise. Give it some love and fix those warnings where it
makes sense. Also make stabilization time a named constant to get rid of
the magic number in clk-cpu.c.
No functional change.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20240224202053.25313-3-semen.protsenko@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
CMU_PERIC1 is the clock management unit used for the peric1 block which
is used for additional USI, I3C and PWM interfaces/busses. Add support
for muxes, dividers and gates of cmu_peric1, except for
CLK_GOUT_PERIC1_IP which isn't well described in the datasheet and
which downstream also ignores (similar to cmu_peric0).
Two clocks have been marked as CLK_IS_CRITICAL for the following
reason:
* disabling them makes it impossible to access any peric1
registers, (including those two registers).
* disabling gout_peric1_lhm_axi_p_peric1_i_clk sometimes has the
additional effect of making the whole system unresponsive.
One clock marked as CLK_IGNORE_UNUSED needs to be kept on until we have
updated the respective driver for the following reason:
* gout_peric1_gpio_peric1_pclk is required by the pinctrl
configuration. With this clock disabled, reconfiguring the pins
(for USI/I2C, USI/UART) will hang during register access.
Since pinctrl-samsung doesn't support a clock at the moment, we
just keep the kernel from disabling it at boot, until we have an
update for pinctrl-samsung, at which point we'll drop the flag.
Signed-off-by: André Draszik <andre.draszik@linaro.org>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Link: https://lore.kernel.org/r/20240201161258.1013664-4-andre.draszik@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
There is an extra empty line here which doesn't exist in any of the
other cmu code blocks in this file.
Drop it to align cmu_top with the rest of the file.
Signed-off-by: André Draszik <andre.draszik@linaro.org>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Link: https://lore.kernel.org/r/20240201161258.1013664-2-andre.draszik@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
When SPI transfer is being prepared, the spi-s3c64xx driver will call
clk_set_rate() to change the rate of SPI source clock (IPCLK). But IPCLK
is a gate (leaf) clock, so it must propagate the rate change up the
clock tree, so that corresponding DIV clocks can actually change their
divider values. Add CLK_SET_RATE_PARENT flag to corresponding clocks for
all SPI instances in Exynos850 (spi_0, spi_1 and spi_2) to make it
possible. This change involves next clocks:
usi_spi_0:
Clock Block Div range
--------------------------------------------
gout_spi0_ipclk CMU_PERI -
dout_peri_spi0 CMU_PERI /1..32
mout_peri_spi_user CMU_PERI -
dout_peri_ip CMU_TOP /1..16
usi_cmgp0:
Clock Block Div range
--------------------------------------------
gout_cmgp_usi0_ipclk CMU_CMGP -
dout_cmgp_usi0 CMU_CMGP /1..32
mout_cmgp_usi0 CMU_CMGP -
gout_clkcmu_cmgp_bus CMU_APM -
dout_apm_bus CMU_APM /1..8
usi_cmgp1:
Clock Block Div range
--------------------------------------------
gout_cmgp_usi1_ipclk CMU_CMGP -
dout_cmgp_usi1 CMU_CMGP /1..32
mout_cmgp_usi1 CMU_CMGP -
gout_clkcmu_cmgp_bus CMU_APM -
dout_apm_bus CMU_APM /1..8
With input clock of 400 MHz, this scheme provides next IPCLK rate range,
for each SPI block:
SPI0: 781 kHz ... 400 MHz
SPI1/2: 1.6 MHz ... 400 MHz
Accounting for internal /4 divider in SPI blocks, and because the max
SPI frequency is limited at 50 MHz, it gives us next SPI SCK rates:
SPI0: 200 kHz ... 49.9 MHz
SPI1/2: 400 kHz ... 49.9 MHz
Which should cover all possible applications of SPI bus. Of course,
setting SPI frequency to values as low as 500 kHz will also affect the
common bus dividers (dout_apm_bus or dout_peri_ip), which in turn
effectively lowers the rates for all leaf bus clocks derived from those
dividers, like HSI2C and I3C clocks. But at least it gives the board
designer a choice, whether to keep all clocks (SPI/HSI2C/I3C) at high
frequencies, or make all those clocks have lower frequencies. Not
propagating the rate change to those common dividers would limit this
choice to "only high frequencies are allowed for SPI/HSI2C/I3C" option,
making the common dividers useless. This decision follows the "Worse is
better" approach, relying on the users/engineers to know the system
internals when working with such low-level features, instead of trying
to account for all possible use-cases.
Fixes: 7dd0557819 ("clk: samsung: Introduce Exynos850 clock driver")
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Link: https://lore.kernel.org/r/20240125013858.3986-2-semen.protsenko@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
This pclk clock is required any time we access the pinctrl registers of
this block.
Since pinctrl-samsung doesn't support a clock at the moment, we just
keep the kernel from disabling it at boot, until we have an update for
pinctrl-samsung to handle this required clock, at which point we'll be
able to drop the flag again.
Signed-off-by: André Draszik <andre.draszik@linaro.org>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20240130093812.1746512-2-andre.draszik@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
CMU_PERIC0 is the clock management unit used for the peric0 block which
is used for USI and I3C. Add support for all cmu_peric0 clocks but
CLK_GOUT_PERIC0_IP (not enough info in the datasheet).
Few clocks are marked as critical because when either of them is
disabled, the system hangs even if their clock parents are enabled.
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Link: https://lore.kernel.org/r/20240122114113.2582612-1-tudor.ambarus@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Update cmu_misc so it is registered early, as it contains
the gate which clocks the Multi Core Timer (MCT). This clock
is required early in boot, otherwise exynos_mct will fail
obtaining the clock.
Note this wasn't previously an issue as exynos_mct wasn't
enabled.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20231222165355.1462740-3-peter.griffin@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
The cmu_misc clock-names were renamed to just "bus" and "sss" because
naming is local to the module, so cmu_misc is implied. As the bindings
and the device tree have not made a release yet, comply with the
renamed clocks.
Suggested-by: Rob Herring <robh@kernel.org>
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Link: https://lore.kernel.org/r/20240109114908.3623645-4-tudor.ambarus@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
SM8650 based on the diffstat. Otherwise this is a collection of non-critical
fixes and cleanups to various clk drivers and their DT bindings. Nothing is
changed in the core clk framework this time, although there's a patch to fix a
basic clk type initialization function. In general, this pile looks to be on
the smaller side.
New Drivers:
- Global, display, gpu, tcsr, and rpmh clocks on Qualcomm SM8650
- Mediatek MT7988 SoC clocks
Updates:
- Update Zynqmp driver for Versal NET platforms
- Add clk driver for Versal clocking wizard IP
- Support for stm32mp25 clks
- Add glitch free PLL setting support to si5351 clk driver
- Add DSI clocks on Amlogic g12/sm1
- Add CSI and ISP clocks on Amlogic g12/sm1
- Document bindings for i.MX93 ANATOP clock driver
- Free clk_node in i.MX SCU driver for resource with different owner
- Update the LVDS clocks to be compatible with i.MX SCU firmware 1.15
- Fix the name of the fvco in i.MX pll14xx by renaming it to fout
- Add EtherNet TSN and PCIe clocks on the Renesas R-Car V4H SoC
- Add interrupt controller and Ethernet clocks and resets on Renesas RZ/G3S
- Check reset monitor registers on Renesas RZ/G2L-alike SoCs
- Reuse reset functionality in the Renesas RZ/G2L clock driver
- Global and RPMh clock support for the Qualcomm X1E80100 SoC
- Support for the Stromer APCS PLL found in Qualcomm IPQ5018
- Add a new type of branch clock, with support for controlling separate
memory control bits, to the Qualcomm clk driver
- Use above new branch type in Qualcomm ECPRI clk driver for QDU1000 and
QRU1000
- Add a number of missing clocks related to CSI2 on Qualcomm MSM8939
- Add support for the camera clock controller on Qualcomm SC8280XP
- Correct PLL configuration in GPU and video clock controllers for
Qualcomm SM8150
- Add runtime PM support and a few missing resets to Qualcomm SM8150
video clock controller
- Fix configuration of various GCC GDSCs on Qualcomm SM8550
- Mark shared RCGs appropriately in the Qualcomm SM8550 GCC driver
- Fix up GPU and display clock controllers PLL configuration settings
on Qualcomm SM8550
- Cleanup variable init in Allwinner nkm module
- Convert various DT bindings to YAML
- A few kernel-doc fixes for Samsung SoC clock controllers
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"Only a couple new SoCs have support added this time, primarily for
Qualcomm SM8650 based on the diffstat. Otherwise this is a collection
of non-critical fixes and cleanups to various clk drivers and their DT
bindings.
Nothing is changed in the core clk framework this time, although
there's a patch to fix a basic clk type initialization function. In
general, this pile looks to be on the smaller side.
New Drivers:
- Global, display, gpu, tcsr, and rpmh clocks on Qualcomm SM8650
- Mediatek MT7988 SoC clocks
Updates:
- Update Zynqmp driver for Versal NET platforms
- Add clk driver for Versal clocking wizard IP
- Support for stm32mp25 clks
- Add glitch free PLL setting support to si5351 clk driver
- Add DSI clocks on Amlogic g12/sm1
- Add CSI and ISP clocks on Amlogic g12/sm1
- Document bindings for i.MX93 ANATOP clock driver
- Free clk_node in i.MX SCU driver for resource with different owner
- Update the LVDS clocks to be compatible with i.MX SCU firmware 1.15
- Fix the name of the fvco in i.MX pll14xx by renaming it to fout
- Add EtherNet TSN and PCIe clocks on the Renesas R-Car V4H SoC
- Add interrupt controller and Ethernet clocks and resets on Renesas
RZ/G3S
- Check reset monitor registers on Renesas RZ/G2L-alike SoCs
- Reuse reset functionality in the Renesas RZ/G2L clock driver
- Global and RPMh clock support for the Qualcomm X1E80100 SoC
- Support for the Stromer APCS PLL found in Qualcomm IPQ5018
- Add a new type of branch clock, with support for controlling
separate memory control bits, to the Qualcomm clk driver
- Use above new branch type in Qualcomm ECPRI clk driver for QDU1000
and QRU1000
- Add a number of missing clocks related to CSI2 on Qualcomm MSM8939
- Add support for the camera clock controller on Qualcomm SC8280XP
- Correct PLL configuration in GPU and video clock controllers for
Qualcomm SM8150
- Add runtime PM support and a few missing resets to Qualcomm SM8150
video clock controller
- Fix configuration of various GCC GDSCs on Qualcomm SM8550
- Mark shared RCGs appropriately in the Qualcomm SM8550 GCC driver
- Fix up GPU and display clock controllers PLL configuration settings
on Qualcomm SM8550
- Cleanup variable init in Allwinner nkm module
- Convert various DT bindings to YAML
- A few kernel-doc fixes for Samsung SoC clock controllers"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (93 commits)
clk: mediatek: add drivers for MT7988 SoC
clk: mediatek: add pcw_chg_bit control for PLLs of MT7988
dt-bindings: clock: mediatek: add clock controllers of MT7988
dt-bindings: reset: mediatek: add MT7988 ethwarp reset IDs
dt-bindings: clock: mediatek: add MT7988 clock IDs
clk: mediatek: mt8188-topckgen: Refactor parents for top_dp/edp muxes
clk: mediatek: mt8195-topckgen: Refactor parents for top_dp/edp muxes
clk: mediatek: clk-mux: Support custom parent indices for muxes
dt-bindings: clock: sophgo: Add clock controller of CV1800 series SoC
clk: starfive: jh7100: Add CLK_SET_RATE_PARENT to gmac_tx
clk: starfive: Add flags argument to JH71X0__MUX macro
clk: imx: pll14xx: change naming of fvco to fout
clk: imx: clk-imx8qxp: fix LVDS bypass, pixel and phy clocks
clk: imx: scu: Fix memory leak in __imx_clk_gpr_scu()
clk: fixed-rate: fix clk_hw_register_fixed_rate_with_accuracy_parent_hw
clk: qcom: dispcc-sm8650: Add test_ctl parameters to PLL config
clk: qcom: gpucc-sm8650: Add test_ctl parameters to PLL config
clk: qcom: dispcc-sm8550: Use the correct PLL configuration function
clk: qcom: dispcc-sm8550: Update disp PLL settings
clk: qcom: gpucc-sm8550: Update GPU PLL settings
...
The gs101 clock defines from the bindings header are derived from the
clock register names found in the datasheet under some certain rules.
The CMU TOP gate clock defines missed to include the required "CMU"
differentiator which will cause collisions with the gate clock defines
of other clock units. Rename the TOP gate clock defines to include "CMU".
Update the clock driver to use the new defines in order to not break
compilation and bisect-ability. There are no device trees that use the
previous defines.
Fixes: 0a910f1606 ("dt-bindings: clock: Add Google gs101 clock management unit bindings")
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20231218064333.479885-1-tudor.ambarus@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
cmu_top is the top level clock management unit which contains PLLs, muxes,
dividers and gates that feed the other clock management units.
cmu_misc clocks IPs such as Watchdog and cmu_apm clocks ips part of the
APM module.
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: André Draszik <andre.draszik@linaro.org>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Tested-by: Will McVicker <willmcvicker@google.com>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20231211162331.435900-9-peter.griffin@linaro.org
[krzysztof: drop not needed linux/of_device.h include]
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
These plls are found in the Tensor gs101 SoC found in the Pixel 6.
pll0516x: Integer PLL with high frequency
pll0517x: Integer PLL with middle frequency
pll0518x: Integer PLL with low frequency
PLL0516x
FOUT = (MDIV * 2 * FIN)/PDIV * 2^SDIV)
PLL0517x and PLL0518x
FOUT = (MDIV * FIN)/PDIV*2^SDIV)
The PLLs are similar enough to pll_0822x that the same code can handle
both. The main difference is the change in the fout formula for the
high frequency 0516 pll.
Locktime for 516,517 & 518 is 150 the same as the pll_0822x lock factor.
MDIV, SDIV PDIV masks and bit shifts are also the same as 0822x.
When defining the PLL the "con" parameter should be set to CON3
register, like this
PLL(pll_0517x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0,
NULL),
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Tested-by: Will McVicker <willmcvicker@google.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20231211162331.435900-8-peter.griffin@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Unify and improve the style of kernel-doc comments in Samsung CCF
framework. Resemble more idiomatic style described in [1] and commonly
used throughout most of the kernel code.
[1] Documentation/doc-guide/kernel-doc.rst
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Acked-by: Randy Dunlap <rdunlap@infradead.org>
Tested-by: Randy Dunlap <rdunlap@infradead.org>
Link: https://lore.kernel.org/r/20231109190925.2066-2-semen.protsenko@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Fix some issues found in kernel-doc comments in Samsung CCF framework.
It makes scripts/kernel-doc happy, which can be checked with:
$ find drivers/clk/samsung/ -name '*.[ch]' -exec \
scripts/kernel-doc -v -none {} \;
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Fixes: ddeac8d968 ("clk: samsung: add infrastructure to register cpu clocks")
Fixes: 721c42a351 ("clk: samsung: add common clock framework helper functions for Samsung platforms")
Fixes: 3ff6e0d8d6 ("clk: samsung: Add support to register rate_table for samsung plls")
Reviewed-by: Randy Dunlap <rdunlap@infradead.org>
Tested-by: Randy Dunlap <rdunlap@infradead.org>
Link: https://lore.kernel.org/r/20231109190925.2066-1-semen.protsenko@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Use preferred device_get_match_data() instead of of_match_device() to
get the driver match data. With this, adjust the includes to explicitly
include the correct headers.
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20231006213959.334439-1-robh@kernel.org
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> #msm part
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> # Samsung
Acked-by: David Lechner <david@lechnology.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
- Add __counted_by to struct clk_hw_onecell_data and struct spmi_pmic_div_clk_cc
- Remove non-OF mmp clk drivers
- Move number of clks from DT headers to drivers
* clk-imx:
clk: imx: pll14xx: dynamically configure PLL for 393216000/361267200Hz
clk: imx: pll14xx: align pdiv with reference manual
clk: imx: composite-8m: fix clock pauses when set_rate would be a no-op
clk: imx25: make __mx25_clocks_init return void
clk: imx25: print silicon revision during init
dt-bindings: clocks: imx8mp: make sai4 a dummy clock
clk: imx8mp: fix sai4 clock
clk: imx: imx8ulp: update SPLL2 type
clk: imx: pllv4: Fix SPLL2 MULT range
clk: imx: imx8: add audio clock mux driver
dt-bindings: clock: fsl,imx8-acm: Add audio clock mux support
clk: imx: clk-imx8qxp-lpcg: Convert to devm_platform_ioremap_resource()
clk: imx: clk-gpr-mux: Simplify .determine_rate()
clk: imx: Add 519.75MHz frequency support for imx9 pll
clk: imx93: Add PDM IPG clk
dt-bindings: clock: imx93: Add PDM IPG clk
* clk-samsung:
dt-bindings: clock: samsung: remove define with number of clocks
clk: samsung: exynoautov9: do not define number of clocks in bindings
clk: samsung: exynos850: do not define number of clocks in bindings
clk: samsung: exynos7885: do not define number of clocks in bindings
clk: samsung: exynos5433: do not define number of clocks in bindings
clk: samsung: exynos5420: do not define number of clocks in bindings
clk: samsung: exynos5410: do not define number of clocks in bindings
clk: samsung: exynos5260: do not define number of clocks in bindings
clk: samsung: exynos5250: do not define number of clocks in bindings
clk: samsung: exynos4: do not define number of clocks in bindings
clk: samsung: exynos3250: do not define number of clocks in bindings
* clk-annotate:
clk: qcom: clk-spmi-pmic-div: Annotate struct spmi_pmic_div_clk_cc with __counted_by
clk: Annotate struct clk_hw_onecell_data with __counted_by
* clk-marvell:
clk: pxa910: Move number of clocks to driver source
clk: pxa1928: Move number of clocks to driver source
clk: pxa168: Move number of clocks to driver source
clk: mmp2: Move number of clocks to driver source
clk: mmp: Remove old non-OF clock drivers
* clk-lmk:
clk: lmk04832: Support using PLL1_LD as SPI readback pin
clk: lmk04832: Don't disable vco clock on probe fail
clk: lmk04832: Set missing parent_names for output clocks
Number of clocks supported by Linux drivers might vary - sometimes we
add new clocks, not exposed previously. Therefore these numbers of
clocks should not be in the bindings, as that prevents changing them.
Define number of clocks per each clock controller inside the driver
directly.
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20230808082738.122804-11-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Number of clocks supported by Linux drivers might vary - sometimes we
add new clocks, not exposed previously. Therefore these numbers of
clocks should not be in the bindings, as that prevents changing them.
Define number of clocks per each clock controller inside the driver
directly.
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20230808082738.122804-10-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Number of clocks supported by Linux drivers might vary - sometimes we
add new clocks, not exposed previously. Therefore these numbers of
clocks should not be in the bindings, as that prevents changing them.
Define number of clocks per each clock controller inside the driver
directly.
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20230808082738.122804-9-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Number of clocks supported by Linux drivers might vary - sometimes we
add new clocks, not exposed previously. Therefore these numbers of
clocks should not be in the bindings, as that prevents changing them.
Define number of clocks per each clock controller inside the driver
directly.
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20230808082738.122804-8-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Number of clocks supported by Linux drivers might vary - sometimes we
add new clocks, not exposed previously. Therefore these numbers of
clocks should not be in the bindings, as that prevents changing them.
Define number of clocks per each clock controller inside the driver
directly.
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20230808082738.122804-7-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Number of clocks supported by Linux drivers might vary - sometimes we
add new clocks, not exposed previously. Therefore these numbers of
clocks should not be in the bindings, as that prevents changing them.
Define number of clocks per each clock controller inside the driver
directly.
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20230808082738.122804-6-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Number of clocks supported by Linux drivers might vary - sometimes we
add new clocks, not exposed previously. Therefore these numbers of
clocks should not be in the bindings, as that prevents changing them.
Define number of clocks per each clock controller inside the driver
directly.
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20230808082738.122804-5-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Number of clocks supported by Linux drivers might vary - sometimes we
add new clocks, not exposed previously. Therefore these numbers of
clocks should not be in the bindings, as that prevents changing them.
Define number of clocks per each clock controller inside the driver
directly.
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20230808082738.122804-4-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Number of clocks supported by Linux drivers might vary - sometimes we
add new clocks, not exposed previously. Therefore these numbers of
clocks should not be in the bindings, as that prevents changing them.
Define number of clocks per each clock controller inside the driver
directly.
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20230808082738.122804-3-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Number of clocks supported by Linux drivers might vary - sometimes we
add new clocks, not exposed previously. Therefore these numbers of
clocks should not be in the bindings, as that prevents changing them.
Define number of clocks per each clock controller inside the driver
directly.
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20230808082738.122804-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
The DT of_device.h and of_platform.h date back to the separate
of_platform_bus_type before it as merged into the regular platform bus.
As part of that merge prepping Arm DT support 13 years ago, they
"temporarily" include each other. They also include platform_device.h
and of.h. As a result, there's a pretty much random mix of those include
files used throughout the tree. In order to detangle these headers and
replace the implicit includes with struct declarations, users need to
explicitly include the correct includes.
Acked-by: Dinh Nguyen <dinguyen@kernel.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> # samsung
Acked-by: Heiko Stuebner <heiko@sntech.de> #rockchip
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com> # versaclock5
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230718143156.1066339-1-robh@kernel.org
Acked-by: Abel Vesa <abel.vesa@linaro.org> #imx
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
When CONFIG_OF is disabled, build testing on x86 runs into a couple of
objtool warnings from functions that unconditionally call panic() but
have no __noreturn annotation:
vmlinux.o: warning: objtool: exynos3250_cmu_isp_probe+0x17: samsung_cmu_register_one() is missing a __noreturn annotation
vmlinux.o: warning: objtool: exynos7885_cmu_probe+0x16: exynos_arm64_register_cmu() is missing a __noreturn annotation
vmlinux.o: warning: objtool: exynos850_cmu_probe+0x16: exynos_arm64_register_cmu() is missing a __noreturn annotation
vmlinux.o: warning: objtool: exynosautov9_cmu_probe+0x16: exynos_arm64_register_cmu() is missing a __noreturn annotation
The objtool analysis is correct, and this could be addressed by just
returning success whenever CONFIG_OF is disabled to let all that code
be eliminated, but since the driver is no use without CONFIG_OF,
just add that as a dependency. It will still get compile tested on
all architectures since CONFIG_OF is enabled in allmodconfig and most
randconfig builds.
Cc: Josh Poimboeuf <jpoimboe@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20230609081559.915867-1-arnd@kernel.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Support for the Exynos4212 SoC was originally dropped as there were
no boards using it. We will be adding a device that uses it, so add
it back.
This reverts commit c9194fb623.
Signed-off-by: Artur Weber <aweber.kernel@gmail.com>
Link: https://lore.kernel.org/r/20230501195525.6268-7-aweber.kernel@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Support for the Exynos4212 SoC was originally dropped as there were
no boards using it. We will be adding a device that uses it, so add
it back.
This reverts commit d5cd103b06.
Signed-off-by: Artur Weber <aweber.kernel@gmail.com>
Link: https://lore.kernel.org/r/20230501195525.6268-6-aweber.kernel@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
PMU_ALIVE_PCLK is needed for PMU registers access, and it must be always
running, as not only the kernel accesses PMU registers. Make it critical
to ensure that.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20230308233822.31180-5-semen.protsenko@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
The .remove() callback for a platform driver returns an int which makes
many driver authors wrongly assume it's possible to do error handling by
returning an error code. However the value returned is (mostly) ignored
and this typically results in resource leaks. To improve here there is a
quest to make the remove callback return void. In the first step of this
quest all drivers are converted to .remove_new() which already returns
void.
Trivially convert this driver from always returning zero in the remove
callback to the void returning variant.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Link: https://lore.kernel.org/r/20230312161512.2715500-25-u.kleine-koenig@pengutronix.de
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Exynos5433 clock driver implements PM support internally, which might be
also useful for other Exynos clock drivers. Extract all PM related code
from clk-exynos5433 to common ARM64 functions.
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20230307002423.24454-4-semen.protsenko@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Extract parent clock enabling from exynos_arm64_register_cmu() to
dedicated function.
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20230307002423.24454-3-semen.protsenko@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
It might be useful to have a separate clocks registration function, so
it can be called from different users. Extract that common code from
samsung_cmu_register_one() to samsung_cmu_register_clocks(). Also make
that new function global as it's going to be used in other modules
further.
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20230307002423.24454-2-semen.protsenko@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Add main gate clocks for controlling AUD and HSI CMUs:
- gout_aud_cmu_aud_pclk
- gout_hsi_cmu_hsi_pclk
Those clocks were marked as CLK_IGNORE_UNUSED, as system hangs on
boot otherwise.
While at it, add missing PPMU (Performance Profiling Monitor Unit)
clocks for CMU_HSI.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Chanho Park <chanho61.park@samsung.com>
Link: https://lore.kernel.org/r/20230223042133.26551-6-semen.protsenko@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
CMU_G3D clock domain provides clocks for Mali-G52 GPU and bus clocks for
BLK_G3D.
This patch adds next clocks:
- bus clocks in CMU_TOP for CMU_G3D
- all internal CMU_G3D clocks
- leaf clocks for GPU, TZPC (TrustZone Protection Controller) and
SysReg
G3D_CMU_G3D clock was marked as CLK_IGNORE_UNUSED, as system hangs on
boot otherwise.
Reviewed-by: Chanho Park <chanho61.park@samsung.com>
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20230223042133.26551-5-semen.protsenko@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
pll0818x PLL is used in Exynos850 SoC for CMU_G3D PLL. Operation-wise,
pll0818x is the same as pll0822x. The only difference is:
- pl0822x is integer PLL with Middle FVCO (950 to 2400 MHz)
- pl0818x is integer PLL with Low FVCO (600 to 1200 MHz)
Add pll0818x type as an alias to pll0822x.
Reviewed-by: Chanho Park <chanho61.park@samsung.com>
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20230223042133.26551-4-semen.protsenko@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Some drivers set dev to context in order to implement PM. Make that part
of samsung_clk_init() instead of assigning `ctx->dev = dev' separately.
No functional change.
Acked-by: Marek Szyprowski <m.szyprowski@samsung.com>
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20230223041938.22732-4-semen.protsenko@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Base address can be derived from context structure. Remove `base'
argument from samsung_clk_register_pll() and use `ctx->reg_base'
instead, as it's done in other clock registering functions.
No functional change.
Acked-by: Marek Szyprowski <m.szyprowski@samsung.com>
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20230223041938.22732-2-semen.protsenko@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
The code using `np' argument was removed from samsung_clk_init(). Remove
that leftover parameter as well.
No functional change.
Fixes: d5e136a21b ("clk: samsung: Register clk provider only after registering its all clocks")
Acked-by: Marek Szyprowski <m.szyprowski@samsung.com>
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20230223041938.22732-3-semen.protsenko@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
The s3c24xx platform is gone, so the clk driver can be removed as
well.
Acked-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
If clk_register() fails, @pll->rate_table may have allocated memory by
kmemdup(), so it needs to be freed, otherwise will cause memory leak
issue, this patch fixes it.
Fixes: 3ff6e0d8d6 ("clk: samsung: Add support to register rate_table for samsung plls")
Signed-off-by: Xiu Jianfeng <xiujianfeng@huawei.com>
Link: https://lore.kernel.org/r/20221123032015.63980-1-xiujianfeng@huawei.com
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
of_device_get_match_data() function should not be used on the device
other than the one matched to the given driver, because it always returns
the match_data of the matched driver. In case of exynos-clkout driver,
the code matched the OF IDs on the PARENT device, so replacing it with
of_device_get_match_data() broke the driver.
This reverts commit 777aaf3d1d.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Fixes: 777aaf3d1d ("clk: samsung: exynos-clkout: Use of_device_get_match_data()")
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20221108213718.32076-1-m.szyprowski@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
"div4" DIVs which divide PLLs by 4 are actually dividing "div2" DIVs by
2 to achieve a by 4 division, thus their parents are the respective
"div2" DIVs. These DIVs were mistakenly set to have the PLLs as parents.
This leads to the kernel thinking "div4"s and everything under them run
at 2x the clock speed. Fix this.
Fixes: 45bd8166a1 ("clk: samsung: Add initial Exynos7885 clock driver")
Signed-off-by: David Virag <virag.david003@gmail.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20221013151341.151208-1-virag.david003@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
CMU_MFCMSCL clock domain provides clocks for MFC (Multi-Format Codec),
JPEG Codec and Scaler IP-cores. According to Exynos850 TRM, CMU_MFCMSCL
generates MFC, M2M, MCSC and JPEG clocks for BLK_MFCMSCL.
This patch adds next clocks:
- bus clocks in CMU_TOP for CMU_MFCMSCL
- all internal CMU_MFCMSCL clocks
- leaf clocks for MFCMSCL, TZPC (TrustZone Protection Controller),
JPEG codec, M2M (Memory-to-Memory), MCSC (Multi-Channel Scaler),
MFC (Multi-Format Codec), PPMU (Platform Performance Monitoring
Unit), SysMMU and SysReg
MFCMSCL related gate clocks in CMU_TOP were marked as CLK_IS_CRITICAL,
because:
1. All of those have to be enabled in order to read
/sys/kernel/debug/clk/clk_summary file
2. When some user driver (e.g. exynos-sysmmu) disables some derived
leaf clock, it can lead to CMU_TOP clocks disable, which then makes
the system hang. To prevent that, the CLK_IS_CRITICAL flag is used,
as CLK_IGNORE_UNUSED is not enough.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220809113323.29965-8-semen.protsenko@linaro.org
CMU_IS clock domain provides clocks for IS IP-core (Image Signal
Processing Subsystem). According to Exynos850 TRM, CMU_IS generates
CSIS, IPP, ITP, VRA and GDC clocks for BLK_IS.
This patch adds next clocks:
- bus clocks in CMU_TOP needed for CMU_IS
- all internal CMU_IS clocks
- leaf clocks for IS IP-core, CSIS (Camera Serial Interface Slave),
D_TZPC (TrustZone Protection Controller), CSIS DMA, GDC (Geometric
Distortion Correction), IPP (Image Preprocessing Processing core),
ITP (Image Texture Processing core), MCSC (Multi-Channel Scaler),
VRA (Visual Recognition Accelerator), PPMU (Platform Performance
Monitoring Unit), SysMMU and SysReg
IS related gate clocks in CMU_TOP were marked as CLK_IS_CRITICAL,
because:
1. All of those have to be enabled in order to read
/sys/kernel/debug/clk/clk_summary file
2. When some user driver (e.g. exynos-sysmmu) disables some derived
leaf clock, it can lead to CMU_TOP clocks disable, which then makes
the system hang. To prevent that, the CLK_IS_CRITICAL flag is used,
as CLK_IGNORE_UNUSED is not enough.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220809113323.29965-7-semen.protsenko@linaro.org
CMU_AUD clock domain provides clocks for ABOX IP-core (audio subsystem).
According to Exynos850 TRM, CMU_AUD generates Cortex-A32 clock, bus
clock and audio clocks for BLK_AUD.
This patch adds next clocks:
- bus clocks in CMU_TOP needed for CMU_AUD
- all internal CMU_AUD clocks
- leaf clocks for Cortex-A32, Speedy FM, UAIF0..UAIF6 (Unified Audio
Interface), CNT (counter), ABOX IP-core, ASB (Asynchronous Bridge),
DAP (Debug Access Port), I2S Codec MCLK, D_TZPC (TrustZone
Protection Controller), GPIO, PPMU (Platform Performance Monitoring
Unit), SysMMU, SysReg and WDT
ABOX clock was marked as CLK_IGNORE_UNUSED, as system hangs on boot
otherwise. Once ABOX driver is implemented, maybe it can be handled
there instead.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220809113323.29965-6-semen.protsenko@linaro.org
Fix some typos in comments and do small coding style improvements.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220809113323.29965-5-semen.protsenko@linaro.org
CMU_FSYS1 provides clocks for USB(2 x USB3.1 Gen-1, 2 x USB 2.0) and
mmc. For MMC clocks, PLL_MMC(PLL0831X type) is also supported as a PLL
source clock provider.
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/d4aa967538fed9667e9550a256e545026fc2fa8d.1659054220.git.chanho61.park@samsung.com
Some register offsets of peric0 and peric1 cmu blocks need to be
corrected and re-ordered by numerical order.
Fixes: f2dd366992 ("clk: samsung: exynosautov9: add cmu_peric0 clock support")
Fixes: b35f27fe73 ("clk: samsung: exynosautov9: add cmu_peric1 clock support")
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220727021357.152421-4-chanho61.park@samsung.com
"gout_peric0_pclk_1" and "gout_peric1_pclk_1" should be added to peric0
and peric1 respectively.
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220727021357.152421-3-chanho61.park@samsung.com
TREX D Core and P core clocks seem to be related to the BTS (Bus Traffic
Shaper) inside the Exynos7885 SoC, and are needed for the SoC to
function correctly.
When clocks are cut from TREX D Core, the eMMC and the framebuffer stops
working properly. Other unknown things may stop working as well.
When clocks are cut from TREX P Core, the system locks up needing a hard
reset.
Add these clocks and mark them critical so that they are always on.
Signed-off-by: David Virag <virag.david003@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220601233743.56317-5-virag.david003@gmail.com
CMU_FSYS clock domain provides clocks for FSYS IP-core providing clocks
for all MMC devices on Exynos7885, and USB30DRD.
Add clocks:
- Bus clocks in CMU_TOP needed for CMU_FSYS
- All clocks in CMU_FSYS needed for MMC devices
Signed-off-by: David Virag <virag.david003@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220601233743.56317-4-virag.david003@gmail.com
Like CMU_PERIC0, this provides clocks for USI06 ~ USI11 and USI_I2C.
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20220504075154.58819-10-chanho61.park@samsung.com
CMU_PERIC0 provides clocks for USI0 ~ USI5 and USIx_I2C. USI0/1/2/3/4/5
have its own divider but USI_I2Cs share "dout_peric0_usi_i2c" divider.
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220504075154.58819-9-chanho61.park@samsung.com
CMU_FSYS2 is responsible to control clocks of BLK_FSYS2 which includes
ufs and ethernet IPs. This patch adds some essential clocks to be
controlled by ethernet/ufs drivers instead of listing full clocks.
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20220504075154.58819-8-chanho61.park@samsung.com
CMU_BUSMC is responsible to control clocks of BLK_BUSMC which represents
Data/Peri buses. Most clocks except PDMA/SPDMA are not necessary to
be controlled by HLOS. So, this adds PDMA/SPDMA gate clocks.
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20220504075154.58819-7-chanho61.park@samsung.com
CMU_PERIS is responsible to control clocks of BLK_PERIS which has
OPT/MCT/WDT and TMU. This patch only supports WDT gate clocks and all
other clocks except WDT will be supported later.
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20220504075154.58819-6-chanho61.park@samsung.com
Add CMU_CORE clock which represents Core BUS clocks. The source clocks
of this CMU block are oscclk or dout_clkcmu_core_bus. Thus, two source
clocks should be provided via device tree. All the gate clocks are
defined as CLK_IS_CRITICAL because they control(gate/ungate) core bus
clocks but not been assigned to any drivers.
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20220504075154.58819-5-chanho61.park@samsung.com
This adds support for CMU_TOP which generates clocks for all the
function blocks such as CORE, FSYS0/1/2, PERIC0/1 and so on. For
CMU_TOP, PLL_SHARED0,1,2,3 and 4 will be the sources of this block
and they will generate bus clocks.
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20220504075154.58819-4-chanho61.park@samsung.com
The Tesla FSD clock controller driver uses shared parts from Exynos
ARM64 clock drivers, so add proper dependency to fix COMPILE_TEST build
errors like:
/usr/bin/aarch64-linux-gnu-ld: drivers/clk/samsung/clk-fsd.o: in function `fsd_cmu_probe':
clk-fsd.c:(.init.text+0x9c): undefined reference to `exynos_arm64_register_cmu'
Reported-by: kernel test robot <lkp@intel.com>
Fixes: e3f3dc3810 ("clk: samsung: fsd: Add cmu_peric block clock information")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Link: https://lore.kernel.org/r/20220129173407.278591-1-krzysztof.kozlowski@canonical.com
Adds clocks for BLK_CAM_CSI block, this is needed for CSI to work.
Cc: linux-fsd@tesla.com
Signed-off-by: Sathyakam M <sathya@samsung.com>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Link: https://lore.kernel.org/r/20220124141644.71052-11-alim.akhtar@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Adds cmu_imem clock related code, imem block contains IPs
like WDT, DMA, TMU etc, these clocks are required for such
IP function.
Cc: linux-fsd@tesla.com
Signed-off-by: Arjun K V <arjun.kv@samsung.com>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Tauseef Nomani <tauseef.n@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Link: https://lore.kernel.org/r/20220124141644.71052-9-alim.akhtar@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
CMU_FSYS0 block has IPs like UFS, EQOS, PCIe etc, lets add
the related clock information for the same.
Cc: linux-fsd@tesla.com
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Shradha Todi <shradha.t@samsung.com>
Signed-off-by: Jayati Sahu <jayati.sahu@samsung.com>
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Link: https://lore.kernel.org/r/20220124141644.71052-7-alim.akhtar@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Add CMU_PERIC block clock information needed for various IPs
functions found in this block.
Cc: linux-fsd@tesla.com
Signed-off-by: Aswani Reddy <aswani.reddy@samsung.com>
Signed-off-by: Niyas Ahmed S T <niyas.ahmed@samsung.com>
Signed-off-by: Chandrasekar R <rcsekar@samsung.com>
Signed-off-by: Jayati Sahu <jayati.sahu@samsung.com>
Signed-off-by: Sriranjani P <sriranjani.p@samsung.com>
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Link: https://lore.kernel.org/r/20220124141644.71052-6-alim.akhtar@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Add initial clock support for FSD (Full Self-Driving) SoC
which is required to bring-up platforms based on this SoC.
Cc: linux-fsd@tesla.com
Signed-off-by: Jayati Sahu <jayati.sahu@samsung.com>
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Link: https://lore.kernel.org/r/20220124141644.71052-5-alim.akhtar@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
This is an initial implementation adding basic clocks, such as UART,
USI, I2C, WDT, ect. and their parent clocks. It is heavily based on the
Exynos850 clock driver at 'drivers/clk/samsung/clk-exynos850.c' which
was made by Sam Protsenko, thus the copyright and author lines were
kept.
Bus clocks are enabled by default as well to avoid hangs while trying to
access CMU registers.
Only the parts of CMU_TOP needed for CMU_CORE and CMU_PERI, a bit of
CMU_CORE, and most of CMU_PERI is implemented as of now.
Signed-off-by: David Virag <virag.david003@gmail.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Link: https://lore.kernel.org/r/20211206153124.427102-7-virag.david003@gmail.com
pll1417x is used in Exynos7885 SoC for top-level integer PLLs.
It is similar enough to pll0822x that practically the same code can
handle both. The difference that's to be noted is that when defining a
pl1417x PLL, the "con" parameter of the PLL macro should be set to the
CON1 register instead of CON3, like this:
PLL(pll_1417x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
PLL_LOCKTIME_PLL_SHARED0, PLL_CON0_PLL_SHARED0,
NULL),
Signed-off-by: David Virag <virag.david003@gmail.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20211206153124.427102-6-virag.david003@gmail.com
Rename exynos850_register_cmu to exynos_arm64_register_cmu and move it
to a new file called "clk-exynos-arm64.c".
This should have no functional changes, but it will allow this code to
be shared between other arm64 Exynos SoCs, like the Exynos7885 and
possibly ExynosAuto V9.
Signed-off-by: David Virag <virag.david003@gmail.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Link: https://lore.kernel.org/r/20211206153124.427102-5-virag.david003@gmail.com
System Register is used to configure system behavior, like USI protocol,
etc. SYSREG clocks should be provided to corresponding syscon nodes, to
make it possible to modify SYSREG registers.
While at it, add also missing PMU and GPIO clocks, which looks necessary
and might be needed for corresponding Exynos850 features soon.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20211217161549.24836-3-semen.protsenko@linaro.org
Some clocks must be registered before init calls. For example MCT clock
(from CMU_PERI) is needed for MCT timer driver, which is registered
with TIMER_OF_DECLARE(). By the time we get to core_initcall() used for
clk-exynos850 platform driver init, it's already too late. Inability to
get "mct" clock in MCT driver leads to kernel panic, as functions
registered with *_OF_DECLARE() can't do deferred calls. MCT timer driver
can't be fixed either, as it's acting as a clock source and it's
essential to register it in start_kernel() -> time_init().
Let's register CMU_PERI clocks early, using CLK_OF_DECLARE(). CMU_TOP
generates clocks needed for CMU_PERI, but it's already registered early.
While at it, let's cleanup the code a bit, by extracting everything
related to CMU initialization and registration to the separate function.
Similar issue was discussed at [1] and addressed in commit 1f7db7bbf0
("clk: renesas: cpg-mssr: Add early clock support"), as well as in
drivers/clk/mediatek/clk-mt2712.c.
[1] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20180829132954.64862-2-chris.brandt@renesas.com/
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Link: https://lore.kernel.org/r/20211122144206.23134-1-semen.protsenko@linaro.org
Some clocks shouldn't be automatically disabled in clk_disable_unused(),
otherwise kernel hangs. Mark those clocks with:
- CLK_IS_CRITICAL flag, when there won't be any consumers for that
clock, but system can't function when it's gated
- CLK_IGNORE_UNUSED flag, when consumer driver will be probably added
later
That makes it possible to run the kernel without passing the
"clk_ignore_unused" param.
Next clocks were modified:
- "gout_dpu_cmu_dpu_pclk": CLK_IGNORE_UNUSED
Will be enabled later in DSIM driver (Display Serial Interface
Master).
- "gout_gpio_peri_pclk": CLK_IGNORE_UNUSED
"gout_gpio_cmgp_pclk": CLK_IGNORE_UNUSED
"gout_gpio_hsi_pclk": CLK_IGNORE_UNUSED
Should be probably enabled in corresponding GPIO driver later, or
made CLK_IS_CRITICAL. "gout_gpio_peri_clk" is actually used by LEDs
on Exynos850-based dev board, so kernel hangs if this clock is not
running. Other clocks were marked as "ignore unused" to prevent
similar issues for other use cases or boards that might be added
later.
- "gout_cci_aclk": CLK_IS_CRITICAL
CCI (Cache Coherent Interconnect): obviously is critical.
- "gout_gic_clk": CLK_IS_CRITICAL
GIC (Generic Interrupt Controller): obviously is critical.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Link: https://lore.kernel.org/r/20211121232741.6967-7-semen.protsenko@linaro.org
CMU_CMGP clock domain provides clocks for CMGP IP-core (Common GPIO).
CMGP module encapsulates next blocks:
- 8 GPIO lines
- 1 GPADC
- 2 USI blocks, each can be configured to provide one of
UART/SPI/HSI2C serial interfaces
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Link: https://lore.kernel.org/r/20211121232741.6967-5-semen.protsenko@linaro.org
