2 Commits

Author	SHA1	Message	Date
Varshini Rajendran	c7f7ddbd27	clk: at91: sam9x7: update pll clk ranges ... Update the min, max ranges of the PLL clocks according to the latest datasheet to be coherent in the driver. This patch solves the issues in configuring the clocks related to peripherals with the desired frequency within the range. Fixes: 33013b43e2 ("clk: at91: sam9x7: add sam9x7 pmc driver") Suggested-by: Patrice Vilchez <Patrice.Vilchez@microchip.com> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com> Link: https://lore.kernel.org/r/20250714093512.29944-1-varshini.rajendran@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>	2025-07-18 09:31:33 +03:00
Varshini Rajendran	33013b43e2	clk: at91: sam9x7: add sam9x7 pmc driver ... Add a driver for the PMC clocks of sam9x7 Soc family. Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com> Link: https://lore.kernel.org/r/20240729070811.1990964-1-varshini.rajendran@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>	2024-08-07 19:16:48 +03:00