Describe perisys-apb4-hclk as the APB clock for TH1520 SoC, which is
essential for accessing GMAC glue registers.
Fixes: 7e756671a6 ("riscv: dts: thead: Add TH1520 ethernet nodes")
Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Drew Fustini <fustini@kernel.org>
Tested-by: Drew Fustini <fustini@kernel.org>
Link: https://patch.msgid.link/20250808093655.48074-5-ziyao@disroot.org
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Add the "gpu-clkgen" reset property to the AON device tree node. This
allows the AON power domain driver to detect the capability to power
sequence the GPU and spawn the necessary pwrseq-thead-gpu auxiliary
driver for managing the GPU's complex power sequence.
This commit also adds the prerequisite
dt-bindings/reset/thead,th1520-reset.h include to make the
TH1520_RESET_ID_GPU_CLKGEN available. This include was previously
dropped during a conflict resolution [1].
Link: https://lore.kernel.org/all/aAvfn2mq0Ksi8DF2@x1/ [1]
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Drew Fustini <drew@pdp7.com>
Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
Signed-off-by: Drew Fustini <drew@pdp7.com>
VO clocks reside in a different address space from the AP clocks on the
T-HEAD SoC. Add the device tree node of a clock-controller to handle
VO address space as well.
Reviewed-by: Drew Fustini <drew@pdp7.com>
Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
Signed-off-by: Drew Fustini <drew@pdp7.com>
T-HEAD TH1520 SoC requires to put the GPU out of the reset state as part
of the power-up sequence.
Link: https://lore.kernel.org/linux-riscv/81e53e3a-5873-44c7-9070-5596021daa42@samsung.com/
Reviewed-by: Drew Fustini <drew@pdp7.com>
Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
[drew: remove hunk that included thead,th1520-reset.h]
Signed-off-by: Drew Fustini <drew@pdp7.com>
The DRM Imagination GPU requires a power-domain driver. In the T-HEAD
TH1520 SoC implements power management capabilities through the E902
core, which can be communicated with through the mailbox, using firmware
protocol.
Add AON node, which servers as a power-domain controller.
Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
Reviewed-by: Drew Fustini <drew@pdp7.com>
Signed-off-by: Drew Fustini <drew@pdp7.com>
Add mailbox device tree node. This work is based on the vendor kernel [1].
Link: https://github.com/revyos/thead-kernel.git [1]
Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
Reviewed-by: Drew Fustini <dfustini@tenstorrent.com>
Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
Add gmac, mdio, and phy nodes to enable the gigabit Ethernet ports on
the BeagleV Ahead and Sipeed Lichee Pi 4a boards.
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
[drew: change apb registers from syscon to second reg of gmac node,
add phy reset delay properties for beaglev ahead]
Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
There are currently no nodes that use spi0 so remove the enabled
property for it in the beaglev ahead and lpi4a dts files. It can be
re-enabled in the future if any peripherals will use it. The definition
of spi0 remains in the th1520.dtsi file.
Suggested-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
The gpio-dwapb looks for clock named "bus" so add clock-names property
for the gpio controller nodes.
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
[dfustini: add two more lines to the commit message]
Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
Add nodes for the 5 user controllable LEDs on the BeagleV Ahead board.
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Tested-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
Add pinctrl settings for UART0 used as the default debug console on
both the Lichee Pi 4A and BeagleV Ahead boards.
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Tested-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
Add names for the GPIO00-GPIO14 lines of the SO-DIMM module.
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Tested-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
Adjust labels for the TH1520 GPIO controllers such that GPIOs can be
referenced by the names used by the documentation. Eg.
GPIO0_X -> <&gpio0 X Y>
GPIO1_X -> <&gpio1 X Y>
GPIO2_X -> <&gpio2 X Y>
GPIO3_X -> <&gpio3 X Y>
GPIO4_X -> <&gpio4 X Y>
AOGPIO_X -> <&aogpio X Y>
Remove labels for the parent GPIO devices that shouldn't need to be
referenced.
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Tested-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
Add gpio-ranges properties to the TH1520 device tree, so user space can
change basic pinconf settings for GPIOs and are not allowed to use pads
already used by other functions.
Adjust number of GPIOs available for the different controllers.
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Tested-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
Add nodes for pin controllers on the T-Head TH1520 RISC-V SoC.
Add the missing aonsys_clk for the always-on pin controller as there is
not yet an aon subsys clock controller driver.
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Tested-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
[dfustini: modify description as there is now an ap_subsys clk driver]
Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
Change the clock property in the TH1520 SPI controller node to a clock
provided by AP_SYS clock controller.
Remove spi_clk fixed clock reference from BeagleV Ahead and LPI4a dts.
Link: https://git.beagleboard.org/beaglev-ahead/beaglev-ahead/-/tree/main/docs
Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
Add clock property to TH1520 gpio controller nodes. These clock gates
refer to corresponding enable bits in the peripheral clock gate control
register. Refer to register PERI_CLK_CFG in section 4.4.2.2.52 of the
TH1520 System User Manual.
Link: https://git.beagleboard.org/beaglev-ahead/beaglev-ahead/-/tree/main/docs
Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
Change the dma-controller and timer nodes to use the APB clock provided
by the AP_SUBSYS clock controller.
Remove apb_clk reference from BeagleV Ahead and LPI4a dts.
Link: https://git.beagleboard.org/beaglev-ahead/beaglev-ahead/-/tree/main/docs
Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
Change the clock property in the TH1520 mmc controller nodes to a clock
provided by AP_SYS clock controller.
Remove sdhci fixed clock reference from BeagleV Ahead and LPI4a dts.
Link: https://git.beagleboard.org/beaglev-ahead/beaglev-ahead/-/tree/main/docs
Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
created spi0 node with fixed clock. the spi0 node
uses synopsis designware driver and has the following
compatible "snps,dw-apb-ssi". the spi0 node is connected
to a SPI NOR flash pad which is left unpopulated on the back
side of the board.
Acked-by: Drew Fustini <drew@pdp7.com>
Signed-off-by: Kanak Shilledar <kanakshilledar@gmail.com>
Signed-off-by: Drew Fustini <drew@pdp7.com>
According to the device tree coding style, nodes shall be ordered by
unit address in ascending order.
Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Add emmc node properties for the eMMC device and add sdio0 node
properties for the microSD slot. Set the frequency for the sdhci
reference clock.
Signed-off-by: Drew Fustini <dfustini@baylibre.com>
Reviewed-by: Guo Ren <guoren@kernel.org>
Reviewed-by: Jisheng Zhang <jszhang@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Add emmc node properties for the eMMC device and add sdio0 node
properties for the microSD slot. Set the frequency for the sdhci
reference clock.
Signed-off-by: Drew Fustini <dfustini@baylibre.com>
Reviewed-by: Guo Ren <guoren@kernel.org>
Reviewed-by: Jisheng Zhang <jszhang@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Add node for the fixed reference clock used for emmc and sdio nodes.
Add emmc node for the 1st dwcmshc instance which is typically connected
to an eMMC device. Add sdio0 node for the 2nd dwcmshc instance which is
typically connected to microSD slot. Add sdio1 node for the 3rd dwcmshc
instance which is typically connected to an SDIO WiFi module. The node
names are based on Table 1-2 C910/C906 memory map in the TH1520 System
User Manual.
Link: https://git.beagleboard.org/beaglev-ahead/beaglev-ahead/-/tree/main/docs
Signed-off-by: Drew Fustini <dfustini@baylibre.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Reviewed-by: Guo Ren <guoren@kernel.org>
Reviewed-by: Jisheng Zhang <jszhang@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
There are a couple new SoCs that are supported for the first time:
- AMD Pensando Elba is a data processing unit based on Cortex-A72
CPU cores
- Sophgo makes RISC-V based chips, and we now support the CV1800B
chip used in the milkv-duo board and the massive sg2042 chip in the
milkv-pioneer, a 64-core developer workstation.
- Qualcomm Snapdragon 720G (sm7125) is a close relative of
Snapdragon 7c and gets added with some Xiaomi phones
- Renesas gains support for the R8A779F4 (R-Car S4-8) automotive
SoC and the RZ/G3S (R9A08G045) embedded SoC.
There are also a bunch of newly supported machines that use
already supported chips. On the 32-bit side, we have:
- USRobotics USR8200 is a NAS/Firewall/router based on the ancient
Intel IXP4xx platform
- A couple of machines based on the NXP i.MX5 and i.MX6 platforms
- One machine each for Allwinner V3s, Aspeed AST2600, Microchip
sama5d29 and ST STM32mp157
The other ones all use arm64 cores on chips from allwinner,
amlogic, freescale, mediatek, qualcomm and rockchip.
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Merge tag 'soc-dt-6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC DT updates from Arnd Bergmann:
"There are a couple new SoCs that are supported for the first time:
- AMD Pensando Elba is a data processing unit based on Cortex-A72 CPU
cores
- Sophgo makes RISC-V based chips, and we now support the CV1800B
chip used in the milkv-duo board and the massive sg2042 chip in the
milkv-pioneer, a 64-core developer workstation.
- Qualcomm Snapdragon 720G (sm7125) is a close relative of Snapdragon
7c and gets added with some Xiaomi phones
- Renesas gains support for the R8A779F4 (R-Car S4-8) automotive SoC
and the RZ/G3S (R9A08G045) embedded SoC.
There are also a bunch of newly supported machines that use already
supported chips. On the 32-bit side, we have:
- USRobotics USR8200 is a NAS/Firewall/router based on the ancient
Intel IXP4xx platform
- A couple of machines based on the NXP i.MX5 and i.MX6 platforms
- One machine each for Allwinner V3s, Aspeed AST2600, Microchip
sama5d29 and ST STM32mp157
The other ones all use arm64 cores on chips from allwinner, amlogic,
freescale, mediatek, qualcomm and rockchip"
* tag 'soc-dt-6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (641 commits)
ARM: dts: BCM5301X: Set switch ports for Linksys EA9200
ARM: dts: BCM5301X: Set fixed-link for extra Netgear R8000 CPU ports
ARM: dts: BCM5301X: Explicitly disable unused switch CPU ports
ARM: dts: BCM5301X: Relicense Vivek's code to the GPL 2.0+ / MIT
ARM: dts: BCM5301X: Relicense Felix's code to the GPL 2.0+ / MIT
ARM: dts: BCM5301X: Set MAC address for Asus RT-AC87U
arm64: dts: socionext: add missing cache properties
riscv: dts: thead: convert isa detection to new properties
arm64: dts: Update cache properties for socionext
arm64: dts: ti: k3-am654-idk: Add ICSSG Ethernet ports
arm64: dts: ti: k3-am654-icssg2: add ICSSG2 Ethernet support
arm64: dts: ti: k3-am65-main: Add ICSSG IEP nodes
arm64: dts: ti: k3-am62p5-sk: Updates for SK EVM
arm64: dts: ti: k3-am62p: Add nodes for more IPs
arm64: dts: rockchip: Add Turing RK1 SoM support
dt-bindings: arm: rockchip: Add Turing RK1
dt-bindings: vendor-prefixes: add turing
arm64: dts: rockchip: Add DFI to rk3588s
arm64: dts: rockchip: Add DFI to rk356x
arm64: dts: rockchip: Always enable DFI on rk3399
...
Convert the th1520 devicetrees to use the new properties
"riscv,isa-base" & "riscv,isa-extensions".
For compatibility with other projects, "riscv,isa" remains.
Reviewed-by: Jisheng Zhang <jszhang@kernel.org>
Acked-by: Guo Ren <guoren@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20231022154135.3746-1-jszhang@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The BeagleV Ahead single board computer uses the T-Head TH1520 SoC.
Add a minimal device tree to support basic uart/gpio/dmac drivers so
that a user can boot to a basic shell.
Link: https://beagleboard.org/beaglev-ahead
Reviewed-by: Guo Ren <guoren@kernel.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Drew Fustini <dfustini@baylibre.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Sipeed's Lichee Pi 4A development board uses Lichee Module 4A core
module which is powered by T-HEAD's TH1520 SoC. Add minimal device
tree files for the core module and the development board.
Support basic uart/gpio/dmac drivers, so supports booting to a basic
shell.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Add initial device tree for the TH1520 RISC-V SoC by T-HEAD.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
