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loongarch-next
1283 Commits
| Author | SHA1 | Message | Date | |
|---|---|---|---|---|
Linus Torvalds
|
4c10d22211 |
soc: defconfig updates for 6.16
As usual, more drivers get enabled in the defconfigs, to support newly added hardware drivers. There is one change for Tegra that modifies the Kconfig file at the same time, and the NXP arm32 defconfigs get a refresh. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmiD8n8ACgkQmmx57+YA GNni9g//d7W04OSpAOCT7LKLhkLEK8CMlAcXJMWSk8cDK0irHtAnmxEiwd/qlfOg bU9oooOd6w5RrLn3A2GCSEMkdW520ng5PlRTKZKpEXr074PI25ghfIf7vfaVrlEN t66P0deO7Yup7SQqa3Wl4V4rcrO6v0w0LKn5nHaajOhTgZhXft4z4fosPegGlez5 lXp9HC7yxLcH8DZkvg8RVRWIZaxnunb1g7P8ma/meqb0jrE9d8JCTU3+I9rHgji3 pqzSAhjnBE/r5dn0IPTMppncJI/hXbqvSf5757osec/9XRfR29/mBfgBT6EUXT6W D2WuHk3DHciitiHrcsTqShMV+R0EUGj7yY4yg0hLXO3Pcdme5pigzJGWUtLczPN3 DayXj7+AJ+G7izdiC+bXI0hqxwKxKc8rkddV0qEWKNI2m69iaGs2xiMF8z6l/asW FYg5t14YN2h2lDpE7Vxo+sey4Dnxqmzel/WkV+UysqqWV5zlGa34ZT66j63m4iLu EYmB4Jw35FMZ6LVCl79q3QtJbusvGlJUHySF+khcEN8WrksNcCVU94mfr08ydsez gpCV+zHyD2z/d5JQVXIAtet/c6DowRy7FggmkauF2IcudDM6lU3WYeKP39fIv/lt w9FddYRMNC+LtnIUccjUcqKkIP3CXJ5zs7qIGflW4qYeRrdSQ0s= =En7k -----END PGP SIGNATURE----- Merge tag 'soc-defconfig-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull SoC defconfig updates from Arnd Bergmann: "As usual, more drivers get enabled in the defconfigs, to support newly added hardware drivers. There is one change for Tegra that modifies the Kconfig file at the same time, and the NXP arm32 defconfigs get a refresh" * tag 'soc-defconfig-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (25 commits) arm: multi_v7_defconfig: Enable TPS65219 regulator arm: omap2plus_defconfig: Enable TPS65219 regulator arm64: defconfig: Enable Tegra241 and Tegra264 riscv: defconfig: spacemit: enable sdhci driver for K1 SoC riscv: defconfig: Enable PWM support for SpacemiT K1 SoC riscv: defconfig: Remove CONFIG_SND_SOC_STARFIVE=m arm64: defconfig: Enable Tegra HSP and BPMP ARM: imx_v6_v7_defconfig: select CONFIG_USB_HSIC_USB3503 ARM: imx_v6_v7_defconfig: select CONFIG_INPUT_PWM_BEEPER ARM: imx_v6_v7_defconfig: cleanup with savedefconfig ARM: mxs_defconfig: select new drivers used by imx28-amarula-rmm ARM: mxs_defconfig: Cleanup mxs_defconfig arm64: defconfig: enable further Rockchip platform drivers arm64: defconfig: enable Samsung PMIC over ACPM arm64: defconfig: enable Maxim max77759 driver ARM: configs: sama5_defconfig: Select CONFIG_WILC1000_SDIO ARM: shmobile: defconfig: Refresh for v6.16-rc2 arm64: defconfig: Enable RZ/V2H(P) USB2 PHY controller reset driver arm64: defconfig: add S32G RTC module support arm64: defconfig: Drop unneeded unselectable sound drivers ... |
||
|
Linus Torvalds
|
4df9c0a246 |
soc: new SoC support for 6.17
These five newly supported chips come with both devicetree descriptions
and the changes to wire them up to the build system for easier bisection.
The chips in question are:
- Marvell PXA1908 was the first 64-bit mobile phone chip from Marvell
in the product line that started with the Digital StrongARM SA1100
based PDAs and continued with the Intel PXA2xx that dominated early
smartphones. This one only made it only into a few products before the
entire product line was cut in 2015.
- The QiLai SoC is made by RISC-V core designer Andes Technologies
and is in the 'Voyager' reference board in MicroATX form factor.
It uses four in-order AX45MP cores, which is the midrange product
from Andes.
- CIX P1 is one of the few Arm chips designed for small workstations,
and this one uses 12 Cortex-A720/A520 cores, making it also one
of the only ARMv9.2 machines that one can but at the moment.
- Axiado AX3000 is an embedded chip with relative small Cortex-A53
CPU cores described as a "Trusted Control/Compute Unit" that can
be used as a BMC in servers. In addition to the usual I/O, this one
comes with 10GBit ethernet and and a 4TOPS NPU.
- Sophgo SG2000 is an embedded chip that comes with both RISC-V
and Arm cores that can run Linux. This was already supported for
RISC-V but now it also works on Arm
One more chip, the Black Sesame C1200 did not make it in tirm for the
merge window.
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Merge tag 'soc-newsoc-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull new SoC support from Arnd Bergmann:
"These five newly supported chips come with both devicetree
descriptions and the changes to wire them up to the build system for
easier bisection.
The chips in question are:
- Marvell PXA1908 was the first 64-bit mobile phone chip from Marvell
in the product line that started with the Digital StrongARM SA1100
based PDAs and continued with the Intel PXA2xx that dominated early
smartphones. This one only made it only into a few products before
the entire product line was cut in 2015.
- The QiLai SoC is made by RISC-V core designer Andes Technologies
and is in the 'Voyager' reference board in MicroATX form factor. It
uses four in-order AX45MP cores, which is the midrange product from
Andes.
- CIX P1 is one of the few Arm chips designed for small workstations,
and this one uses 12 Cortex-A720/A520 cores, making it also one of
the only ARMv9.2 machines that one can but at the moment.
- Axiado AX3000 is an embedded chip with relative small Cortex-A53
CPU cores described as a "Trusted Control/Compute Unit" that can be
used as a BMC in servers. In addition to the usual I/O, this one
comes with 10GBit ethernet and and a 4TOPS NPU.
- Sophgo SG2000 is an embedded chip that comes with both RISC-V and
Arm cores that can run Linux. This was already supported for RISC-V
but now it also works on Arm
One more chip, the Black Sesame C1200 did not make it in tirm for the
merge window"
* tag 'soc-newsoc-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (38 commits)
arm64: defconfig: Enable rudimentary Sophgo SG2000 support
arm64: Add SOPHGO SOC family Kconfig support
arm64: dts: sophgo: Add Duo Module 01 Evaluation Board
arm64: dts: sophgo: Add Duo Module 01
arm64: dts: sophgo: Add initial SG2000 SoC device tree
MAINTAINERS: Add entry for Axiado
arm64: defconfig: enable the Axiado family
arm64: dts: axiado: Add initial support for AX3000 SoC and eval board
arm64: add Axiado SoC family
dt-bindings: i3c: cdns: add Axiado AX3000 I3C controller
dt-bindings: serial: cdns: add Axiado AX3000 UART controller
dt-bindings: gpio: cdns: add Axiado AX3000 GPIO variant
dt-bindings: gpio: cdns: convert to YAML
dt-bindings: arm: axiado: add AX3000 EVK compatible strings
dt-bindings: vendor-prefixes: Add Axiado Corporation
MAINTAINERS: Add CIX SoC maintainer entry
arm64: dts: cix: Add sky1 base dts initial support
dt-bindings: clock: cix: Add CIX sky1 scmi clock id
arm64: defconfig: Enable CIX SoC
mailbox: add CIX mailbox driver
...
|
||
|
Linus Torvalds
|
115e74a29b |
soc: dt changes for 6.17
There are a few new variants of existing chips:
- mt6572 is an older mobile phone chip from mediatek that was
extremely popular a decade ago but never got upstreamed until now.
- exynos2200 is a recent high-end mobile phone chip used in a
few Samsung phones like the Galaxy S22
- Renesas R-Car V4M-7 (R8A779H2) is an updated version of R-Car V4M
(R8A779H0) and used in automotive applications
- Tegra264 is a new chip from NVIDIA, but support is fairly minimal
for now, and not much information is public about it.
There are five more chips in a separate branch, as those are new
chip families that I merged along with the necessary infrastructure.
New board support is not that exciting, with a total of 33 newly
added machines here:
- Evaluation platforms for the chips above, plus TI am62d2 and
Sophgo sg2042.
- Six 32-bit industrial boards based on stm32, imx6 and am33 chips,
plus eight 64-bit rockchips rk33xx/rk35xx, am62d2, t527, imx8 and
imx95.
- Two newly added ASPEED BMC based motherboards, and one that got
removed
- Phones and Tablets based on 32-bit mt6572, tegra30 and 64-bit
msm8976 SoCs
- Three Laptops based on Mediatek mt8186 and Qualcomm Snapdragon X1
- A set-top box based on Amlogic meson-gxm.
Updates for existing machines are spread over all the above families.
One notable change here is support for the RP1 I/O chip used in
Raspberry Pi 5.
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Merge tag 'soc-dt-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC devicetree updates from Arnd Bergmann:
"There are a few new variants of existing chips:
- mt6572 is an older mobile phone chip from mediatek that was
extremely popular a decade ago but never got upstreamed until now
- exynos2200 is a recent high-end mobile phone chip used in a few
Samsung phones like the Galaxy S22
- Renesas R-Car V4M-7 (R8A779H2) is an updated version of R-Car V4M
(R8A779H0) and used in automotive applications
- Tegra264 is a new chip from NVIDIA, but support is fairly minimal
for now, and not much information is public about it
There are five more chips in a separate branch, as those are new chip
families that I merged along with the necessary infrastructure.
New board support is not that exciting, with a total of 33 newly added
machines here:
- Evaluation platforms for the chips above, plus TI am62d2 and Sophgo
sg2042
- Six 32-bit industrial boards based on stm32, imx6 and am33 chips,
plus eight 64-bit rockchips rk33xx/rk35xx, am62d2, t527, imx8 and
imx95
- Two newly added ASPEED BMC based motherboards, and one that got
removed
- Phones and Tablets based on 32-bit mt6572, tegra30 and 64-bit
msm8976 SoCs
- Three Laptops based on Mediatek mt8186 and Qualcomm Snapdragon X1
- A set-top box based on Amlogic meson-gxm
Updates for existing machines are spread over all the above families.
One notable change here is support for the RP1 I/O chip used in
Raspberry Pi 5"
* tag 'soc-dt-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (606 commits)
riscv: dts: sophgo: fix mdio node name for CV180X
riscv: dts: sophgo: sophgo-srd3-10: reserve uart0 device
riscv: dts: sophgo: add Sophgo SG2042_EVB_V2.0 board device tree
riscv: dts: sophgo: add Sophgo SG2042_EVB_V1.X board device tree
dt-bindings: riscv: add Sophgo SG2042_EVB_V1.X/V2.0 bindings
riscv: dts: sophgo: add ethernet GMAC device for sg2042
riscv: dts: sophgo: Enable ethernet device for Huashan Pi
riscv: dts: sophgo: Add mdio multiplexer device for cv18xx
riscv: dts: sophgo: Add ethernet device for cv18xx
riscv: dts: sophgo: sg2044: add pmu configuration
riscv: dts: sophgo: sg2044: add ziccrse extension
riscv: dts: sophgo: add zfh for sg2042
riscv: dts: sophgo: add ziccrse for sg2042
riscv: dts: sophgo: Add xtheadvector to the sg2042 devicetree
riscv: dts: sophgo: sg2044: add PCIe device support for SG2044
riscv: dts: sophgo: sg2044: add MSI device support for SG2044
riscv: dts: sophgo: add reset configuration for Sophgo CV1800 series SoC
riscv: dts: sophgo: add reset generator for Sophgo CV1800 series SoC
dt-bindings: soc: sophgo: Move SoCs/boards from riscv into soc, add SG2000
riscv: dts: sophgo: sg2044: Add missing riscv,cbop-block-size property
...
|
||
|
Linus Torvalds
|
13150742b0 |
Crypto library updates for 6.17
This is the main crypto library pull request for 6.17. The main focus
this cycle is on reorganizing the SHA-1 and SHA-2 code, providing
high-quality library APIs for SHA-1 and SHA-2 including HMAC support,
and establishing conventions for lib/crypto/ going forward:
- Migrate the SHA-1 and SHA-512 code (and also SHA-384 which shares
most of the SHA-512 code) into lib/crypto/. This includes both the
generic and architecture-optimized code. Greatly simplify how the
architecture-optimized code is integrated. Add an easy-to-use
library API for each SHA variant, including HMAC support. Finally,
reimplement the crypto_shash support on top of the library API.
- Apply the same reorganization to the SHA-256 code (and also SHA-224
which shares most of the SHA-256 code). This is a somewhat smaller
change, due to my earlier work on SHA-256. But this brings in all
the same additional improvements that I made for SHA-1 and SHA-512.
There are also some smaller changes:
- Move the architecture-optimized ChaCha, Poly1305, and BLAKE2s code
from arch/$(SRCARCH)/lib/crypto/ to lib/crypto/$(SRCARCH)/. For
these algorithms it's just a move, not a full reorganization yet.
- Fix the MIPS chacha-core.S to build with the clang assembler.
- Fix the Poly1305 functions to work in all contexts.
- Fix a performance regression in the x86_64 Poly1305 code.
- Clean up the x86_64 SHA-NI optimized SHA-1 assembly code.
Note that since the new organization of the SHA code is much simpler,
the diffstat of this pull request is negative, despite the addition of
new fully-documented library APIs for multiple SHA and HMAC-SHA
variants. These APIs will allow further simplifications across the
kernel as users start using them instead of the old-school crypto API.
(I've already written a lot of such conversion patches, removing over
1000 more lines of code. But most of those will target 6.18 or later.)
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Merge tag 'libcrypto-updates-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/ebiggers/linux
Pull crypto library updates from Eric Biggers:
"This is the main crypto library pull request for 6.17. The main focus
this cycle is on reorganizing the SHA-1 and SHA-2 code, providing
high-quality library APIs for SHA-1 and SHA-2 including HMAC support,
and establishing conventions for lib/crypto/ going forward:
- Migrate the SHA-1 and SHA-512 code (and also SHA-384 which shares
most of the SHA-512 code) into lib/crypto/. This includes both the
generic and architecture-optimized code. Greatly simplify how the
architecture-optimized code is integrated. Add an easy-to-use
library API for each SHA variant, including HMAC support. Finally,
reimplement the crypto_shash support on top of the library API.
- Apply the same reorganization to the SHA-256 code (and also SHA-224
which shares most of the SHA-256 code). This is a somewhat smaller
change, due to my earlier work on SHA-256. But this brings in all
the same additional improvements that I made for SHA-1 and SHA-512.
There are also some smaller changes:
- Move the architecture-optimized ChaCha, Poly1305, and BLAKE2s code
from arch/$(SRCARCH)/lib/crypto/ to lib/crypto/$(SRCARCH)/. For
these algorithms it's just a move, not a full reorganization yet.
- Fix the MIPS chacha-core.S to build with the clang assembler.
- Fix the Poly1305 functions to work in all contexts.
- Fix a performance regression in the x86_64 Poly1305 code.
- Clean up the x86_64 SHA-NI optimized SHA-1 assembly code.
Note that since the new organization of the SHA code is much simpler,
the diffstat of this pull request is negative, despite the addition of
new fully-documented library APIs for multiple SHA and HMAC-SHA
variants.
These APIs will allow further simplifications across the kernel as
users start using them instead of the old-school crypto API. (I've
already written a lot of such conversion patches, removing over 1000
more lines of code. But most of those will target 6.18 or later)"
* tag 'libcrypto-updates-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/ebiggers/linux: (67 commits)
lib/crypto: arm64/sha512-ce: Drop compatibility macros for older binutils
lib/crypto: x86/sha1-ni: Convert to use rounds macros
lib/crypto: x86/sha1-ni: Minor optimizations and cleanup
crypto: sha1 - Remove sha1_base.h
lib/crypto: x86/sha1: Migrate optimized code into library
lib/crypto: sparc/sha1: Migrate optimized code into library
lib/crypto: s390/sha1: Migrate optimized code into library
lib/crypto: powerpc/sha1: Migrate optimized code into library
lib/crypto: mips/sha1: Migrate optimized code into library
lib/crypto: arm64/sha1: Migrate optimized code into library
lib/crypto: arm/sha1: Migrate optimized code into library
crypto: sha1 - Use same state format as legacy drivers
crypto: sha1 - Wrap library and add HMAC support
lib/crypto: sha1: Add HMAC support
lib/crypto: sha1: Add SHA-1 library functions
lib/crypto: sha1: Rename sha1_init() to sha1_init_raw()
crypto: x86/sha1 - Rename conflicting symbol
lib/crypto: sha2: Add hmac_sha*_init_usingrawkey()
lib/crypto: arm/poly1305: Remove unneeded empty weak function
lib/crypto: x86/poly1305: Fix performance regression on short messages
...
|
||
|
Arnd Bergmann
|
05a623030b |
ARM Devicetrees for v6.17
Sophgo: Add support for Duo Module 01 Evaluation Board. This board uses SG2000(old codename CV181xH), which is dual-arch, RISC-V and ARM64. This patch add the support for ARM64. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> -----BEGIN PGP SIGNATURE----- iQGzBAABCgAdFiEEdoBX2jyDC9ZCTwZjDCzASqG0i0IFAmiAiNIACgkQDCzASqG0 i0KaPgv/Zbe5hJ869PocVXmt1+lHnMMh6bTANXlZO4G3NcjBOvCWF9rZaqY7Tb0w ekLbSTnhBqcwix62FxDuOubsgAGrj/r5ejnPkLI/Ksst+81DDcgtxmU4YHjV/M92 win6fsrS5LppqS7+6lGAhN0Uz48K07j9URW2JtollpH0GyrzNo1r4YwfkUA38X+b e+Eia0bvz8KU1aKPLgmx+dk/qjhDvvlWjNrroVyJAkUYM5AofSSzneo2hgM6FA0k 1LYZRwLDpbaJjMnBvAFT2Dqg3Mr+84PyHb7d+58lV4BYOzkA/wM6DGuDqD61dt4K +pxflhrZsXp+a9SjnY6oecGy1srKDPhX8l6mRdwt3ISAFJ/6nKTEXk36sO1T9atq mfpwDwDklhVwpvmk9JAWeTCX/XMBgivVDdUE9sRTzBqPIlBtSVHjS8W7e5nExbv8 yovIIKE4OLKn40ubcYM8Km0L3XF6VpoNFlPkxwrXDyf7FVzdHTphz0aW8CXIO0dP 4W1vqUcP =v6O6 -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmiBQ8MACgkQmmx57+YA GNmgUQ/+JJHLhDUdfI6abJSs42ZS7yue8DRbSYi/h3RDkj7LutwbrTrOZ7Dg0uom txv2dUPtmW2DIvJkRrBfNeF9bMt9oh0/0cLuf9QL8mLWHaSg9aAwmBDbw8EaKCy1 iwxwAhRxDg1bF6eB0QDE0f2+wuBBiR2ymWcpLgHw3pZw1Ao7R8nvV0UvrxUKJaMa 8GpenYRnVrxHtwtSLS+eFQUvxFGb8SYdHxhZYL3U34XduugK3xNv2+KoFdQvro6R vEMnpR6USo2mV4RW7GTwJkPmQ/w0fMZF806bPNu7KhrC3DLmVnU6YuBDopJYrPvU babwfughoSn7cz733gDSPuzkoNkjXiCZLQW9wSv+gGgYHK6NpjtHfZGkEfcRpXT1 G9Yb/H948BtLM4FxenFh+5VEvp63giN3hTIw/0JauFWEu4rTmN6sMLT1ibLDeUZV zIfItosgFF+EjuGqgruR8dJ9wKowIR9DY8MxhWQ5Wu1WNl+KKMtln/bFIu9hgvRi 0WqgqPr6Vq5buHKaqHAz0tj8dR7yxBZvDijQfzzb0xrLgBXx35c7aX1aKWdxWbYZ Y29KQLxsvr0AWs0tafmQ42M0l03QAB1voACn25rIQaU4b4Tub9W18GkA0V6Mmjno diqH51MQy1haCJRZUMEyAUnmtOXlRw685Jzy1z5BekUJIhTGQfg= =SQbL -----END PGP SIGNATURE----- Merge tag 'arm-sophgo-dt-for-v6.17' of https://github.com/sophgo/linux into soc/newsoc ARM Devicetrees for v6.17 Sophgo: Add support for Duo Module 01 Evaluation Board. This board uses SG2000(old codename CV181xH), which is dual-arch, RISC-V and ARM64. This patch add the support for ARM64. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * tag 'arm-sophgo-dt-for-v6.17' of https://github.com/sophgo/linux: arm64: defconfig: Enable rudimentary Sophgo SG2000 support arm64: Add SOPHGO SOC family Kconfig support arm64: dts: sophgo: Add Duo Module 01 Evaluation Board arm64: dts: sophgo: Add Duo Module 01 arm64: dts: sophgo: Add initial SG2000 SoC device tree Link: https://lore.kernel.org/r/MAUPR01MB11072C4B088AAC02268044E95FE5FA@MAUPR01MB11072.INDPRD01.PROD.OUTLOOK.COM Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Alexander Sverdlin
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fe4fd70193 |
arm64: defconfig: Enable rudimentary Sophgo SG2000 support
Enable ARCH_SOPHGO, pinctrl (built-in, required to boot), ADC as module. This defconfig is able to boot from SD card on Milk-V Duo Module 01 evalboard. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com> Link: https://lore.kernel.org/r/20250612132844.767216-7-alexander.sverdlin@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn> |
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Arnd Bergmann
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5cfe03e1ca |
Enable Rockchip DFI + PM_DEVFREQ_EVENT and RGA modules.
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Arnd Bergmann
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4252ec9ff8 |
Qualcomm Arm64 defconfig updates for v6.17
Enable camera and video clock controllers for SM8450, SM8550, and SM8650 platforms. -----BEGIN PGP SIGNATURE----- iQJJBAABCAAzFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmh8XlAVHGFuZGVyc3Nv bkBrZXJuZWwub3JnAAoJEAsfOT8Nma3FQ6sP/0SIviiM6A4a+N7zr02VQCwQdRPl U4mqeo74UcVdLrvHBtAQ+H7r+mC2Gff9JdFUggS16MtnpdT7qLNVZgxr+ABMJ73m VqwN/TXoXgOYNaap1gUTbpDpkZ8Di1IgbyABzSvmegdEawJbppYZdEEnkbfeEFk5 XMQDZltSSQbavQJo2kacMsiVe14MRI/iQy1zXnF10nRL77pPLTz/5aY9x66Q/L5k 1whQsllClID/ofWZUKHyqmpXvKc7l6ALsvIUcMATV8ZhC5Ih7USJi7tVicZLr9nW /FmfGkilsOwgoK/wxG/07LdWvmnRntsSl6RjVkDF+QQd1u96r9I0WaGvc6gnExLk aTsRQod8sM/xBMGWWr0icLClg2wauyFer6nu9FNfWVCOO4/R4Dhv/VJz3J1YUC1O X73BpFHxzrkPlkIq6auHtem28BGihnfpCki8XwbfgjokVbNh/5lX8ErcQvmzp5ZU LKjANasNEXPMTy6JX/DxqV4ca867VWJlgGOJ4ZYbFL58v6qJCNup9N38RGMqchvq 5blD2hv8PaM0Mdov8Dk8cEfRU3uexKMxqqs5rHGSplyIc1QmAvOr5CGJXPBvshQp oAbRbPNdDXiuwabKzZ+B+C/Lmo+snf6Pt/j06dKFu5ou1gEECsPmkNZx0zy1iPBt ySfVH/Ijcahp+0VX =1NO+ -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmh/+w8ACgkQmmx57+YA GNlRLw/+IZDdP/UHyNGywLJB8r9quJg+/8G6fAilAj0gqsN0tpeNhHjzMAeyAorY y3wa3MpilyFoc7OCj5/k+rSWrFdD3Alk7g9r81mgXn5Sgh2OzrPra0IBKm7kaWm8 5L1v4R9IibWrqS4U18HIDJJ7fgg+TKe05jdR8UxFAb4PaA+wCZ1PS6twaaVlJjo7 aGY876ht0vXeJgfJPjQjhULnFet4c/EZLuFK0CYCyFXViqhtJRryZwU6TYPIzzp0 7V8zy/n4lVY7L+kS6c0tNfy56ju3FE+iO2CFZYONAR/iv1BNaEyt76nzmAP6YjIz oHAyMy/YgfO/DpdOU5ffAHTLMxelOuSSwV7RMFL+B25h/gA1eZuZz2q8z7L+h9+l kTVwJTcsxT+heirQC6zlCpZ+Spp09y8HABLkd2nXraiZzVb6VsgokSbVr7nuLIhe aSuCWBq5JSxm5/r00TEoJ3eP7k3KpTDsAf41VvXBzUoJOpBXWN0J8fol76kJGbu/ Pj2gHLveH4IabmC/MX3x5CvuBO8jBDXb21/mBxKgDRNoTNOEbUYkFn4Zv+gCEDbD fq+siyjkYLNO7qk/pZjQqNJjgX0RozdDs5QuCpBA7osOxLAhyDSObceE/mkHFTpw 9siIM3VQPmVE18pzqcvMZSidN6bWW0WcjSHzoRnJAfN0bXD5jOo= =XhSP -----END PGP SIGNATURE----- Merge tag 'qcom-arm64-defconfig-for-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/defconfig Qualcomm Arm64 defconfig updates for v6.17 Enable camera and video clock controllers for SM8450, SM8550, and SM8650 platforms. * tag 'qcom-arm64-defconfig-for-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: arm64: defconfig: Enable camcc and videocc on Qualcomm SM8450+ Link: https://lore.kernel.org/r/20250720031134.286063-1-andersson@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Arnd Bergmann
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dceb36675b |
Merge branch 'newsoc/axiado' into soc/newsoc
Support for the AX3000 SoC, from Harshit Shah <hshah@axiado.com>: The AX3000 is a multi-core system-on-chip featuring four ARM Cortex-A53 cores, secure vault, hardware firewall, and AI acceleration engines. This initial support enables basic bring-up of the SoC and evaluation platform with CPU, timer, UART, and I3C functionality. The series begins by adding the "axiado" vendor prefix and compatible strings for the SoC and board. It then introduces the device tree files and minimal ARCH_AXIADO platform support in arm64. * newsoc/axiado: MAINTAINERS: Add entry for Axiado arm64: defconfig: enable the Axiado family arm64: dts: axiado: Add initial support for AX3000 SoC and eval board arm64: add Axiado SoC family dt-bindings: i3c: cdns: add Axiado AX3000 I3C controller dt-bindings: serial: cdns: add Axiado AX3000 UART controller dt-bindings: gpio: cdns: add Axiado AX3000 GPIO variant dt-bindings: gpio: cdns: convert to YAML dt-bindings: arm: axiado: add AX3000 EVK compatible strings dt-bindings: vendor-prefixes: Add Axiado Corporation |
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Harshit Shah
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525f46c7e3 |
arm64: defconfig: enable the Axiado family
Enable the Axiado SoC family in the arm64 defconfig. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Harshit Shah <hshah@axiado.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Arnd Bergmann
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c18b21c5d5 |
i.MX defconfig changes for 6.17:
- Enable S32G RTC driver as module in arm64 defconfig - Enable drivers used by imx28-amarula-rmm board in mxs_defconfig - Enable INPUT_PWM_BEEPER, USB_HSIC_USB3503 and BT_HCIUART_BCM in imx_v6_v7_defconfig -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEEFmJXigPl4LoGSz08UFdYWoewfM4FAmhzSLUACgkQUFdYWoew fM6fYQf/Tg4aRk0Z7YyQS1InW8bIOdswvvIelpGEUEOfYhOolvGCAemHeU4eT5Bs M82S8n6Ntbsu9TcAB/Q7Gp5W8Wu4wF4I83HiwykJ2WQuLLGXRGT6yQNYDycPAJbR 43LtNqvavBcAnnz5CXqCoQ4OQ1hVLhYUHiWtWBTCZ+0Lv12JE0Sfo4fkj9HGy/ym fpHOrKaB00yLBO/O0tALAfp8Poct9VUJLXlnVqy5BBMNvNVvL7I1ZpoPRlwk2Gdv lshhQahgIOIErHrtMYk7izZyb3sVci8Gq9COuwv5OYruxDBY2cCfYCHmff9m3Ef8 W36NoETUj15uCHk/ijcy3TcDrB+1+A== =J9v5 -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmh/8+MACgkQmmx57+YA GNnRfg//dPrM1foO5avKnNdvNPuC5ZWjeVMPIqX2r0waV7rCgZiBJCdnbTzunfSi VgyJsNYEQ+jE4g/LUFQLJeHweCkretYG5Y6FpmU9i2KdXIvomVPOlihLVEHAciEk d98rNcsCb8hCxRo/kvKHeeKiQ9nTlAPjNe87tbrZ3I+UdIe6rR+V4ZJ49gKAIs3J AiR8Ez7JegLjgNGVVVa96tKFvXOG7YmgQhJBslulg0/A1QHgbr3sWdflsBLJnrr1 SaNXuviEZisZm5GUG0e+qtxKfPWXkA0OSnFzfw5DEImd0VF3m4mTAiC2Wo3L9vS9 zvhmf71ohGqSPBZ5Vh0DO12xuNeNYTWoB0U6xZDT8X8z8hK2qU9zXNwFoa7pmIdh RzxkeT4lflviT0YglFtPglmv7iEar2NHpbLpWKXt/x2Ozq50+honcNb7EgEAyPFp QFM98B5pgnmw4RD/8L1hmD2ZdEMOBdPPz+TAD1JPwC1jU16XfaM+P0QgWvo72iQW xdAvNlBuJCJO7fpTpVOzsnAZ0IQT7t9r96AgKHj+oEW+101B0AT79Cq1HnP/tkmm ewDXW8DoVkgiYz/HkdeKP8AxvYyS7LKtvI3IPAw0YrctTzkR6PICJ0fqIkLnWEXY 6+bkIcskNLOsyJALfmHioTXDaymxjkQEPxwMtKmpuuo4Ag6Lfc8= =CHlJ -----END PGP SIGNATURE----- Merge tag 'imx-defconfig-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/defconfig i.MX defconfig changes for 6.17: - Enable S32G RTC driver as module in arm64 defconfig - Enable drivers used by imx28-amarula-rmm board in mxs_defconfig - Enable INPUT_PWM_BEEPER, USB_HSIC_USB3503 and BT_HCIUART_BCM in imx_v6_v7_defconfig * tag 'imx-defconfig-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: ARM: imx_v6_v7_defconfig: select CONFIG_USB_HSIC_USB3503 ARM: imx_v6_v7_defconfig: select CONFIG_INPUT_PWM_BEEPER ARM: imx_v6_v7_defconfig: cleanup with savedefconfig ARM: mxs_defconfig: select new drivers used by imx28-amarula-rmm ARM: mxs_defconfig: Cleanup mxs_defconfig arm64: defconfig: add S32G RTC module support ARM: imx_v6_v7_defconfig: Select BT_HCIUART_BCM Link: https://lore.kernel.org/r/20250713055441.221235-5-shawnguo2@yeah.net Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Arnd Bergmann
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0570e9064c |
arm64: tegra: Default configuration updates for v6.17-rc1
Enable the HSP and BPMP via the configuration instead of selecting them, which can lead to problems. Also enable support for Tegra241, which was never done after support for it was added, and Tegra264. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAmhxir0ACgkQ3SOs138+ s6FhJBAAmnjQOaQPOsmwTXRZcYERrvAw2opyVNhifDvhaf5CSb8y0Qq2/Sp8jraW 7odU3jSxEy+DDKscAhIseequMs8VyAHtkgeOcQ+VS2XXiJJq7B0m5X5Hso470cdr hwnooio6Ljh9+S6t6gF7kF9vp1dZSl1JTdCqUGl6qJCAGcS2dfEc+YRZss40pyWt p3NQiLnCpmWqo2te9VzUKOFsotOO0WtrVbwQ6qnwv8as3pzNfcK230OlpwKtkesn oGqqgr1/cvXH1LSNZzQqZoZdNbQNuvvZbr7Lc0cOjeRmo7/2s1DDr6uq5DdqaXok aG1ozW7HaIoaPSGPFULZF/1mt7Po/W/g7LaWaNIsqksTSJ2ye9c25T8qh4517Iq/ nyrsZxaXtXNah9PmwOiV3p5dPr1o3buvbyvWuIhW0jzdV6CcZQcG1q+yvvUJ2wDp dunaQA8of4PnGbsTI6QX6NyBuZ8+xfXuj8Lbjzp7JCha+GXkXzQ94Oxt1lZQORNv aggSg/T5ORAaXTJxYiyD5Zqf2sCsIMl8ZxOTJ9KySvOmBBr3Y7cnrTL1aJotIw0r 73b2As1NR7K24/VzmX2pvYbIpNmihsdid4SkAoxX24FQ7Mg2GCKqzOB9guFhQ0is ri9U3GvuCMtnDD4O49jo83QM6CSWSVp36e2oOG/ACUpqAE785Ks= =ARB0 -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmh/80cACgkQmmx57+YA GNmo9Q//fx+345Q7e7cRIXQc6WcLk35tpJ6Rp5AZ2DWF3gLR91sN3O5f63bZ3sb3 f2TFIj/inusc7ph6wh7GVA1aGQhW4ADWb4vrhEyHmCIMRCQ1tbeyOg8rm1AmiaJe 0nQIFR2m3i1dltgB8DW+ueQ7WnutV09uok/A1wPu4NXFVktVLOQHjp+C0M5SuAsT 6uCqctBaMGpQlnTP8KhnsdSF1VCItowHkSJ26zX9ALmV8t9eweAtwGsWy8oV8id4 IdsUDQ4Id0Ba4wWLdru0j6aNsSr6Jt6uPbX/WpCQ7/z/+IePTHvDLHdvTNTELmSz kMLrqWZZTO77wi1Im02IERbA3ltJJTeSgBWt8AGSBq5XCD5Ti2yFoOBWrSp6Bg5x IJDc3CbJX6s/U8e7grHBOU+w+sk38VcuelRkGCdsI5jo1Lglan7fN5n3/dnOrwn8 Q9YVi5BY7CU57559tI7np8sI1tZP3En9UBpKzJFfquu274xSGoLZWgspTt1d57t1 2pyPsh24lE0mgfYmTLTE50PLJbchagMwya0s0psJNJTmCmrMru0nssShdMzuWFDT +Ehz+7twHLqRXiHzXFCdDk0MMdZb6Q2Wz95VWxEWeQNwu+SV58jlz/QtE3f8BBRD h0i8zoLFGenVaCPrXiOuJg9f6mKnadEY/9uVghehZEMWfhcwky0= =OiJ2 -----END PGP SIGNATURE----- Merge tag 'tegra-for-6.17-arm64-defconfig' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/defconfig arm64: tegra: Default configuration updates for v6.17-rc1 Enable the HSP and BPMP via the configuration instead of selecting them, which can lead to problems. Also enable support for Tegra241, which was never done after support for it was added, and Tegra264. * tag 'tegra-for-6.17-arm64-defconfig' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: arm64: defconfig: Enable Tegra241 and Tegra264 arm64: defconfig: Enable Tegra HSP and BPMP Link: https://lore.kernel.org/r/20250711220943.2389322-8-thierry.reding@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Arnd Bergmann
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1e1bf8bf4e |
Samsung SoC defconfig changes for v6.17
1. Multiple SoCs (including Samsung, Apple): switch sound to module from
a built-in, because it is not necessary for booting. Also drop
redundant sound codec options.
2. Enable PMIC drivers for Google GS101 Pixel 6 phones: MAX77759 and
Samsung PMIC over ACPM protocol.
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Merge tag 'samsung-defconfig-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/defconfig
Samsung SoC defconfig changes for v6.17
1. Multiple SoCs (including Samsung, Apple): switch sound to module from
a built-in, because it is not necessary for booting. Also drop
redundant sound codec options.
2. Enable PMIC drivers for Google GS101 Pixel 6 phones: MAX77759 and
Samsung PMIC over ACPM protocol.
* tag 'samsung-defconfig-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: defconfig: enable Samsung PMIC over ACPM
arm64: defconfig: enable Maxim max77759 driver
arm64: defconfig: Drop unneeded unselectable sound drivers
arm64: defconfig: Switch SOUND to module
Link: https://lore.kernel.org/r/20250709191523.171359-4-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
||
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Arnd Bergmann
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c5b9bff35a
|
Merge branch 'newsoc/cix-p1' into soc/newsoc
Patches from Peter Chen <peter.chen@cixtech.com>: Cixtech P1 (internal name sky1) is high performance generic Armv9 SoC. Orion O6 is the Arm V9 Motherboard built by Radxa. You could find brief introduction for SoC and related boards at: https://radxa.com/products/orion/o6#overview Currently, to run upstream kernel at Orion O6 board, you need to use BIOS released by Radxa, and add "clk_ignore_unused=1" at bootargs. https://docs.radxa.com/en/orion/o6/bios/install-bios In this series, we add initial SoC and board support for Kernel building. Since mailbox is used for SCMI clock communication, mailbox driver is added in this series for the minimum SoC support. Patch 1-2: add dt-binding doc for CIX and its sky1 SoC Patch 3: add Arm64 build support Patch 4-5: add CIX mailbox driver which needs to support SCMI clock protocol. Patch 6: add Arm64 defconfig support Patch 7-8: add initial dts support for SoC and Orion O6 board Patch 9: add MAINTAINERS entry * newsoc/cix-p1: MAINTAINERS: Add CIX SoC maintainer entry arm64: dts: cix: Add sky1 base dts initial support dt-bindings: clock: cix: Add CIX sky1 scmi clock id arm64: defconfig: Enable CIX SoC mailbox: add CIX mailbox driver dt-bindings: mailbox: add cix,sky1-mbox arm64: Kconfig: add ARCH_CIX for cix silicons dt-bindings: arm: add CIX P1 (SKY1) SoC dt-bindings: vendor-prefixes: Add CIX Technology Group Co., Ltd. Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
||
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Peter Chen
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4cd122a4f6 |
arm64: defconfig: Enable CIX SoC
- Enable CIX SoC support at ARM64 defconfig - Enable CIX mailbox At CIX SoC platforms, the clock handling uses Arm SCMI protocol, the physical clock access is at sub processor, so it needs to enable mailbox by default. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Peter Chen <peter.chen@cixtech.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
||
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Eric Biggers
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00d549bb89 |
lib/crypto: arm64/sha1: Migrate optimized code into library
Instead of exposing the arm64-optimized SHA-1 code via arm64-specific crypto_shash algorithms, instead just implement the sha1_blocks() library function. This is much simpler, it makes the SHA-1 library functions be arm64-optimized, and it fixes the longstanding issue where the arm64-optimized SHA-1 code was disabled by default. SHA-1 still remains available through crypto_shash, but individual architectures no longer need to handle it. Remove support for SHA-1 finalization from assembly code, since the library does not yet support architecture-specific overrides of the finalization. (Support for that has been omitted for now, for simplicity and because usually it isn't performance-critical.) To match sha1_blocks(), change the type of the nblocks parameter and the return value of __sha1_ce_transform() from int to size_t. Update the assembly code accordingly. Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Link: https://lore.kernel.org/r/20250712232329.818226-9-ebiggers@kernel.org Signed-off-by: Eric Biggers <ebiggers@kernel.org> |
||
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Arnd Bergmann
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8f0837fdc5 |
Qualcomm Arm64 defconfig fixes for v6.16
The v6.16 driver and DeviceTree updates described and implemented CPU frequency scaling for the Qualcomm X Elite platform. But the necessary CPUCP mailbox driver was not enabled, resulting in a series of error messages being logged during boot (and no CPU frequency scaling). Enable the missing drivers to silence the errors, and enable CPU frequency scaling on this platform. -----BEGIN PGP SIGNATURE----- iQJJBAABCAAzFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmhv/yAVHGFuZGVyc3Nv bkBrZXJuZWwub3JnAAoJEAsfOT8Nma3Fq8QQAJ7O/pDAH1Qy775bmF6ZBpHPN+3D aEpVBBxv9Pv5UhGdTnaOn8HFvfn19R6UNt0TqK1q6RZou10kzbZQQsBDqThWpajQ R1aSLqpVOYBbWeg+YAzKNlMt3Lphu0ewSpGCvOReUJMEaQv33HzJCBwvp9W+oMi9 BAfvjoO22S5epSr114eKKrRCJsyDNQz3P2rg0rSKnhDiTs2Le1g+3O459XWzyGc9 dm264CnNszjTnvg9fLSMU9XJifEObNlg2v/iRwWL1B1A802skMJoxTJv2kE4RB+9 G1ZjnLCYphm8taO1RojhW0RCNzOQ40iLXurklxVmO14hNOwRJWrfedxPanaw5R7Y HqQIH/8mNs+j1eDtWC2zArxkkBwWGyyrzFCHt1WV83PKUJRvbMwobeylB63ecC6w XUBf3guIyU22i6wS38abxAlGfO7Zo2POxehamf0Oab66TkGmSLukd2KuYsAof6TD t5B8MiPchJWFQhPbdOcXD7GhTL0OgnwsxQxbo02o6i3C7lWNNqPigSQ7dGKjnoL4 kvZIftEfLXLwU1wFpxtXccdRQr1idHJ3XhyAeIAYiqDl+AkpMRJuwUNLpUFvTbWQ qDp3YPBlsAMHkj+CxsdA9OdAGanC+fMB/6HKGRnXzcJonbca+G2x9zwuBb0KT/G5 5foLJzNqCFK+vLWf =eirM -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmhw+FcACgkQmmx57+YA GNnvhxAAkG6ZWjDHHMnwDjNHwctopaS/3NQhIwfYKRxXxzmPiWAubBLDfoj5+STg SYkSXG4AK47dPNAYVipDfa6Jjfvq4nlgB68ZPV0vYJ/iwvFXe5fMw7Rkcx3jQ8ok gszz2MRfsfO+NcbhxcJsq5Y5fafjKa04xFgECz14HPkm9tgivw5DsMeeYkbbU1Ea vLSjtu+iYY6DtW2An216vZvTc+CfjV50YJtLwhoZY4s/dJ3WnW0ScI/Ecb52Iwog O/epa8XwHT2ONRhCiaj4K/od5GXj989CBzajaZN5+SlizJ4KYoa2VRdJlrjgVJs9 8JiMYSxLkjqMwrQeZhIGa43sDcKCdlfuhtngn5fxnfUdGWB47kmtSHcU8tSRI99i IpHyPxM4g+0CzRlJd4Z0ZC3Ket6o465KODIBTrlQ34Er5vbQHW/oaUq4IK3z3D0K jovnkh4EBNiAASqMD+k+FyLTfv5P6Ieeo8KI/8KRFzUAKV7x96B3d4m36AyGjPvE ypYbBSz9j1P2hivqe1HgNx1VNAE5i4EUSLrGWuijbBjwC9wNSDne5lPcgJzEvPza ivwOj14QKweoY+FPinRWjOL/sQuxOqwLw39giV/pbMeinhWUSPeR0HrTWgBJvt0e eHL+SS4YE79h2tLu981SeZ9cH2Nfv/pY0OBe/6HuQRQh/7FESX4= =2Ewt -----END PGP SIGNATURE----- Merge tag 'qcom-arm64-defconfig-fixes-for-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/fixes Qualcomm Arm64 defconfig fixes for v6.16 The v6.16 driver and DeviceTree updates described and implemented CPU frequency scaling for the Qualcomm X Elite platform. But the necessary CPUCP mailbox driver was not enabled, resulting in a series of error messages being logged during boot (and no CPU frequency scaling). Enable the missing drivers to silence the errors, and enable CPU frequency scaling on this platform. * tag 'qcom-arm64-defconfig-fixes-for-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: arm64: defconfig: Enable Qualcomm CPUCP mailbox driver Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
||
|
Thierry Reding
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bd3b8e53e2 |
arm64: defconfig: Enable Tegra241 and Tegra264
Enable the configuration options for these newer generations of Tegra so that support for them gets built by default. Link: https://lore.kernel.org/r/20250709231401.3767130-5-thierry.reding@gmail.com Signed-off-by: Thierry Reding <treding@nvidia.com> |
||
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Thierry Reding
|
18c590e012 |
arm64: defconfig: Enable Tegra HSP and BPMP
Selecting the IVC, HSP and BPMP drivers via Kconfig is problematic because it can create conflicting configurations. Instead, enable them in the default configuration. Link: https://lore.kernel.org/r/20250506133118.1011777-12-thierry.reding@gmail.com Signed-off-by: Thierry Reding <treding@nvidia.com> |
||
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Patrice Chotard
|
0000061550 |
arm64: defconfig: Enable STM32 Octo Memory Manager and OcstoSPI driver
Enable STM32 OctoSPI driver. Enable STM32 Octo Memory Manager (OMM) driver which is needed for OSPI usage on STM32MP257F-EV1 board. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20250630-upstream_omm_ospi_defconfig-v11-1-6e934fabe698@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> |
||
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Fabrice Gasnier
|
9259e150de |
arm64: defconfig: enable STM32 timers drivers
Enable the STM32 timer drivers: MFD, counter, PWM and trigger as module. These drivers can be used on STM32MP25. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Link: https://lore.kernel.org/r/20250110091922.980627-6-fabrice.gasnier@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> |
||
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Arnd Bergmann
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241a3be477 |
This pull request contains ARM64 defconfig updates for 6.17, please pull
the following: - Andrea updates the defconfig to enable the RP1 misc, clock and gpio drivers as as well as turn on CONFIG_OF_OVERLAY which is necessary to apply the RP1 overlay file -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEm+Rq3+YGJdiR9yuFh9CWnEQHBwQFAmhi3aIACgkQh9CWnEQH BwSl7xAAupOJhfLuzCvJFciZrEZdys1oJSiM5awzvLk/kpddyzTUUBJG+x9/X/C5 VqyHB4nF2Y9p05DNWEzP/kCZni6jCbi2pPobcmimTKj0eTJDhTImYzxiDptkR9e3 sdyBj+DHqIymKdeCYaQDgDxzvp3v+kdZQ95dE+D2ILOKNXaUEYXswEbGap6r6Iwp olV12hVOcfTARiJToi43+aK5UQn24D0qPEeDQstj+MidNnAQAKLuydSrWbdW60U5 33VX7stPnXW1ul7DuQAa1DFIRJCfdkJAboGVEaDSzQWcGfEYq3UPcCl9M0T098/9 6PARnq8we5ElLPH8morvCOZd9I4beYJB74Kka178/hYj+sQo5IsM0b5CCoHlokq4 t8TnzomBnJu4qPBaA6lnRHff30PtEkSoH7b1es4PqcKd8z1gcWBPCzSfp7Rp12vw do9YIrz+blM71str+wXptJS4ndj/hhasJoWM7Da0edVpHAPebrvMXixdy9og9ZNl lKDmWOYmQwBanE5ZOKVSd0apx8MVy4XWdNQvYBGcPZDJdrMD5e8QZIQfnV8d5c0C mJHtwYiuYcWx4WK87vEL2bFJQXW0ilvSNvoUTNYw6dcz+PIiALDGJ1rHyrWGrFTe QAExbZ6sjTkt53JOsxu+CB+2OndXAPAKV7X/KCBSzgtFCfqBiWU= =1iLu -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmhncNEACgkQmmx57+YA GNnx2A//RzSAFoB2U+3KtH9I571FkQj8c/r07vSMGeCLwBfIui+EC++QoBIWIRY5 cwmblXJZDx22vkpYxPyMgfNOo8LELOnWfuR+yR2uBTzrojFqvj1nXStoDmuJiF3w 0ZuM0cBHZVDzCGBzwcac8MFvvY6KUJ81ySFPEt5iCBgLcHyKAhG8SaEQCDzTqexl jPRDlQTUupwotID4QTjdiyP3IAl9Tg4HfMPmDlzwUGEuLBOFXI98zXKpku390ehV 6K+DuLeq4zfVhDzEMHCljDQ8VawB/zd2VYYUqagOrrgazjnCm7dCOo7N+TwXFLMq FxuDdvM9ea0qguRwrghrcKa3F3YeoQmqUtOsxbzJPikkaTyF2cN1BEuytpCJ7wYJ 3fqojeOy3G7b674VSKukjm3juyYjsPAlbXd/xuSDAP7E0smwVbl1ikUDmD1uZQhv W2oEEw3DFkyhTAcIf51O14hlIqWF0wqqsVxl/tnNF1TjwQbDZ1Egw+nAa62koSd3 oFZozI27znJxYUrNFi6Gsv7i2npT1I9TKaCgXPvEkWPEeriu+r51B91j/NctFOnV PqLaM6ZbVm2mp/THAwlutPOnf/5vLxn79Yg0FqDimwJPHQtNpuJx7vvqo/AG/WkD 9vc1DQlEAGXQt6ygkeuTec83Eji/RzUVpAcw3K85npneIJTg9p8= =eRjS -----END PGP SIGNATURE----- Merge tag 'arm-soc/for-6.17/defconfig-arm64' of https://github.com/Broadcom/stblinux into soc/defconfig This pull request contains ARM64 defconfig updates for 6.17, please pull the following: - Andrea updates the defconfig to enable the RP1 misc, clock and gpio drivers as as well as turn on CONFIG_OF_OVERLAY which is necessary to apply the RP1 overlay file * tag 'arm-soc/for-6.17/defconfig-arm64' of https://github.com/Broadcom/stblinux: arm64: defconfig: Enable OF_OVERLAY option arm64: defconfig: Enable RP1 misc/clock/gpio drivers Link: https://lore.kernel.org/r/20250630190216.1518354-1-florian.fainelli@broadcom.com Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Eric Biggers
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60e3f1e9b7 |
lib/crypto: arm64/sha512: Migrate optimized SHA-512 code to library
Instead of exposing the arm64-optimized SHA-512 code via arm64-specific crypto_shash algorithms, instead just implement the sha512_blocks() library function. This is much simpler, it makes the SHA-512 (and SHA-384) library functions be arm64-optimized, and it fixes the longstanding issue where the arm64-optimized SHA-512 code was disabled by default. SHA-512 still remains available through crypto_shash, but individual architectures no longer need to handle it. To match sha512_blocks(), change the type of the nblocks parameter of the assembly functions from int or 'unsigned int' to size_t. Update the ARMv8 CE assembly function accordingly. The scalar assembly function actually already treated it as size_t. Acked-by: Ard Biesheuvel <ardb@kernel.org> Link: https://lore.kernel.org/r/20250630160320.2888-9-ebiggers@kernel.org Signed-off-by: Eric Biggers <ebiggers@kernel.org> |
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Nicolas Frattaroli
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edc4a9d1dc |
arm64: defconfig: enable further Rockchip platform drivers
Enable the rockchip-dfi driver as a module, which is used on RK3588 as well as RK3568 and RK3399 to measure memory bandwidth. For this, we also enable PM_DEVFREQ_EVENT, which is a requirement for this driver. Also enable the rockchip-rga driver as a module, which is used on various Rockchip SoCs, including RK3588 and RK3399, to provide 2d accelerated image transformations through a V4L2 interface. Suggested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20250626-rk3588-defconfig-v2-1-ae6720964b01@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de> |
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André Draszik
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a7d7aebed4 |
arm64: defconfig: enable Samsung PMIC over ACPM
Enable the Samsung s2mpg1x driver as this is used by the gs101-oriole and gs101-raven (Google Pixel 6 and Pixel 6 Pro) boards. It communicates over ACPM instead of I2C, hence the additional defconfig item. Signed-off-by: André Draszik <andre.draszik@linaro.org> Link: https://lore.kernel.org/r/20250627-gs101-reboot3-v1-1-c3ae49657b1f@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
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André Draszik
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ffdf3c7769 |
arm64: defconfig: enable Maxim max77759 driver
Enable the Maxim max77759 as this is used by the gs101-oriole and gs101-raven (Google Pixel 6 and Pixel 6 Pro) boards, The child devices' defaults are based on this MFD driver's state, so this commit enables those implicitly as well. Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20250524-b4-max77759-mfd-dts-v2-1-b479542eb97d@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
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Lad Prabhakar
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41cffe6d23 |
arm64: defconfig: Enable RZ/V2H(P) USB2 PHY controller reset driver
Enable the `CONFIG_RESET_RZV2H_USB2PHY` option in the arm64 defconfig to support the USB2 PHY controller reset driver on the Renesas RZ/V2H(P) SoC, as used on the RZ/V2H EVK board. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250513125858.251064-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> |
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Ciprian Marian Costea
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322892937b |
arm64: defconfig: add S32G RTC module support
The RTC hardware module present on S32G based SoCs tracks clock time during system suspend and it is used as a wakeup source on S32G2/S32G3 architecture. Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org> |
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Krzysztof Kozlowski
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a8365bfb24 |
arm64: defconfig: Drop unneeded unselectable sound drivers
SND_SOC_ES8328 is selected by SND_SOC_ES8328_I2C. SND_SOC_WCD939X is selected by SND_SOC_WCD939X. None of these are user-visible options so their presence in defconfig is redundant. Link: https://lore.kernel.org/r/20250612134421.95782-4-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
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Krzysztof Kozlowski
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927f1259c5 |
arm64: defconfig: Switch SOUND to module
Sound drivers are not essential to boot boards or mount rootfs, therefore in effort to reduce the size of kernel image (and boot images) switch the ASoC drivers to modules to decrease the size: vmlinux: 154528 kB -> 152864 kB Image: 39391 kB -> 39067 kB No difference in resulting include/generated/autoconf.h, except making modules: SND_SOC_SAMSUNG, SND_SOC_SDCA_OPTIONAL, SND_SOC_APPLE_MCA, SND_TIMER, SND_COMPRESS_OFFLOAD, SND_PCM, SND_SOC_SOF_OF and SND_DMAENGINE_PCM. Suggested-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Sven Peter <sven@kernel.org> Link: https://lore.kernel.org/r/20250612134421.95782-3-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
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Krzysztof Kozlowski
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c5d02bbaa2 |
arm64: defconfig: Enable camcc and videocc on Qualcomm SM8450+
Enable the drivers for camera clock controllers on Qualcomm SM8550 and SM8650 SoC (enabled in all DTS files like SM8550-HDK or SM8650-HDK) and video clock controllers on Qualcomm SM8450 SoC (enabled in SM8450-HDK DTS). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250605173608.217495-2-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org> |
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Casey Connolly
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f17d5b9094 |
arm64: defconfig: update renamed PHY_SNPS_EUSB2
This config option was renamed, update the defconfig to match.
Fixes:
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Bjorn Andersson
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3871b51a68 |
arm64: defconfig: Enable Qualcomm CPUCP mailbox driver
The Qualcomm CPUCP mailbox driver needs to be enabled for CPU frequency scaling to work on the X Elite platform, so enable this driver. Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250605-enable-cpucp-v1-1-111ecef7e4c9@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> |
||
|
Andrea della Porta
|
44bba869d2 |
arm64: defconfig: Enable OF_OVERLAY option
The RP1 driver uses the infrastructure enabled by OF_OVERLAY config option. Enable that option in defconfig in order to produce a kernel usable on RaspberryPi5 avoiding to enable it separately. Signed-off-by: Andrea della Porta <andrea.porta@suse.com> Reviewed-by: Stefan Wahren <wahrenst@gmx.net> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Link: https://lore.kernel.org/r/20250529135052.28398-12-andrea.porta@suse.com Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com> |
||
|
Andrea della Porta
|
67cb34423a |
arm64: defconfig: Enable RP1 misc/clock/gpio drivers
Select the RP1 drivers needed to operate the PCI endpoint containing several peripherals such as Ethernet and USB Controller. This chip is present on RaspberryPi 5. Signed-off-by: Andrea della Porta <andrea.porta@suse.com> Reviewed-by: Stefan Wahren <wahrenst@gmx.net> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Link: https://lore.kernel.org/r/20250529135052.28398-11-andrea.porta@suse.com Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com> |
||
|
Linus Torvalds
|
69352bd52b |
MFD for v6.16
* Samsung Exynos ACPM:
* Populate child platform devices from device tree data
* Introduce a new API, `devm_acpm_get_by_node()`, for child devices to get the ACPM handle
* ROHM PMICs:
* Add support for the ROHM BD96802 scalable companion PMIC to the BD96801 core driver
* Add support for controlling the BD96802 using the BD96801 regulator driver
* Add support to the BD96805, which is almost identical to the BD96801
* Add support to the BD96806, which is similar to the BD96802
* Maxim MAX77759:
* Add a core driver for the MAX77759 companion PMIC
* Add a GPIO driver for the expander functions on the MAX77759
* Add an NVMEM driver to expose the non-volatile memory on the MAX77759
* STMicroelectronics STM32MP25:
* Add support for the STM32MP25 SoC to the stm32-lptimer
* Add support for the STM32MP25 to the clocksource driver, handling new register access requirements
* Add support for the STM32MP25 to the PWM driver, enabling up to two PWM outputs
* Broadcom BCM590xx:
* Add support for the BCM59054 PMU
* Parse the PMU ID and revision to support behavioral differences between chip revisions
* Add regulator support for the BCM59054
* Samsung S2MPG10:
* Add support for the S2MPG10 PMIC, which communicates via the Samsung ACPM firmware instead of I2C
* Exynos ACPM:
* Improve timeout detection reliability by using ktime APIs instead of a loop counter assumption
* Allow PMIC access during late system shutdown by switching to `udelay()` instead of a sleeping function
* Fix an issue where reading command results longer than 8 bytes would fail
* Silence non-error `-EPROBE_DEFER` messages during boot to clean up logs
* Exynos LPASS:
* Fix an error handling path by switching to `devm_regmap_init_mmio()` to prevent resource leaks
* Fix a bug where `exynos_lpass_disable()` was called twice in the remove function
* Fix another resource leak in the probe's error path by using `devm_add_action_or_reset()`
* Samsung SEC:
* Handle the s2dos05, which does not have IRQ support, explicitly to prevent warnings
* Fix the core driver to correctly handle errors from `sec_irq_init()` instead of ignoring them
* STMPE-SPI:
* Correct an undeclared identifier in the `MODULE_DEVICE_TABLE` macro
* MAINTAINERS:
* Adjust a file path for the Siemens IPC LED drivers entry to fix a broken reference
* Maxim Drivers:
* Correct the spelling of "Electronics" in Samsung copyright headers across multiple files
* General:
* Fix wakeup source memory leaks on device unbind for 88pm886, as3722, max14577, max77541, max77705,
max8925, rt5033, and sprd-sc27xx drivers
* Samsung SEC Drivers:
* Split the driver into a transport-agnostic core (`sec-core`) and transport-specific (`sec-i2c`,
`sec-acpm`) modules to support non-I2C devices
* Merge the `sec-core` and `sec-irq` modules to reduce memory consumption
* Move internal APIs to a private header to clean up the public API
* Improve code style by sorting includes, cleaning up headers, sorting device tables, and using helper
macros like `dev_err_probe()`, `MFD_CELL`, and `REGMAP_IRQ_REG`
* Make regmap configuration for s2dos05/s2mpu05 explicit to improve clarity
* Rework platform data and regmap instantiation to use OF match data instead of a large switch statement
* ROHM BD96801/2:
* Prepare the driver for new models by separating chip-specific data into its own structure
* Drop IC name prefix from IRQ resource names in both the MFD and regulator drivers for simplification
* Broadcom BCM590xx:
* Refactor the regulator driver to store descriptions in a table to ease support for new chips
* Rename BCM59056-specific data to prepare for the addition of other regulators
* Use `dev_err_probe()` for cleaner error handling
* Exynos ACPM:
* Correct kerneldoc warnings and use the conventional 'np' argument name
* General MFD:
* Convert `aat2870` and `tps65010` to use the per-client debugfs directory provided by the I2C core
* Convert `sm501`, `tps65010` and `ucb1x00` to use the new GPIO line value setter callbacks
* Constify `regmap_irq_chip` and other structures in `88pm886` to move data to read-only sections
* BCM590xx:
* Drop the unused "id" member from the `bcm590xx` struct in preparation for a replacement
* Samsung SEC Core:
* Remove forward declarations for functions that no longer exist
* SM501:
* Remove the unused `sm501_find_clock()` function
* New Compatibles:
* Google: Add a PMIC child node to the `google,gs101-acpm-ipc` binding
* ROHM: Add new bindings for `rohm,bd96802-regulator` and `rohm,bd96802-pmic`, and add compatibles
for BD96805 and BD96806
* Maxim: Add new bindings for `maxim,max77759-gpio`, `maxim,max77759-nvmem`, and the top-level
`maxim,max77759`
* STM: Add `stm32mp25` compatible to the `stm32-lptimer` binding
* Broadcom: Add `bcm59054` compatible
* Atmel/Microchip: Add `microchip,sama7d65-gpbr` and `microchip,sama7d65-secumod` compatibles
* Samsung: Add `s2mpg10` compatible to the `samsung,s2mps11` MFD binding
* MediaTek: Add compatibles for `mt6893` (scpsys), `mt7988-topmisc`, and `mt8365-infracfg-nao`
* Qualcomm: Add `qcom,apq8064-mmss-sfpb` and `qcom,apq8064-sps-sic` syscon compatibles
* Refactoring & Cleanup:
* Convert Broadcom BCM59056 devicetree bindings to YAML and split them into MFD and regulator parts
* Convert the Microchip AT91 secumod binding to YAML
* Drop unrelated consumer nodes from binding examples to reduce bloat
* Correct indentation and style in various DTS examples
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Merge tag 'mfd-next-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd
Pull MFD updates from Lee Jones:
"Samsung Exynos ACPM:
- Populate child platform devices from device tree data
- Introduce a new API, 'devm_acpm_get_by_node()', for child devices
to get the ACPM handle
ROHM PMICs:
- Add support for the ROHM BD96802 scalable companion PMIC to the
BD96801 core driver
- Add support for controlling the BD96802 using the BD96801 regulator
driver
- Add support to the BD96805, which is almost identical to the
BD96801
- Add support to the BD96806, which is similar to the BD96802
Maxim MAX77759:
- Add a core driver for the MAX77759 companion PMIC
- Add a GPIO driver for the expander functions on the MAX77759
- Add an NVMEM driver to expose the non-volatile memory on the
MAX77759
STMicroelectronics STM32MP25:
- Add support for the STM32MP25 SoC to the stm32-lptimer
- Add support for the STM32MP25 to the clocksource driver, handling
new register access requirements
- Add support for the STM32MP25 to the PWM driver, enabling up to two
PWM outputs
Broadcom BCM590xx:
- Add support for the BCM59054 PMU
- Parse the PMU ID and revision to support behavioral differences
between chip revisions
- Add regulator support for the BCM59054
Samsung S2MPG10:
- Add support for the S2MPG10 PMIC, which communicates via the
Samsung ACPM firmware instead of I2C
Exynos ACPM:
- Improve timeout detection reliability by using ktime APIs instead
of a loop counter assumption
- Allow PMIC access during late system shutdown by switching to
'udelay()' instead of a sleeping function
- Fix an issue where reading command results longer than 8 bytes
would fail
- Silence non-error '-EPROBE_DEFER' messages during boot to clean up
logs
Exynos LPASS:
- Fix an error handling path by switching to
'devm_regmap_init_mmio()' to prevent resource leaks
- Fix a bug where 'exynos_lpass_disable()' was called twice in the
remove function
- Fix another resource leak in the probe's error path by using
'devm_add_action_or_reset()'
Samsung SEC:
- Handle the s2dos05, which does not have IRQ support, explicitly to
prevent warnings
- Fix the core driver to correctly handle errors from
'sec_irq_init()' instead of ignoring them
STMPE-SPI:
- Correct an undeclared identifier in the 'MODULE_DEVICE_TABLE' macro
MAINTAINERS:
- Adjust a file path for the Siemens IPC LED drivers entry to fix a
broken reference
Maxim Drivers:
- Correct the spelling of "Electronics" in Samsung copyright headers
across multiple files
General:
- Fix wakeup source memory leaks on device unbind for 88pm886,
as3722, max14577, max77541, max77705, max8925, rt5033, and
sprd-sc27xx drivers
Samsung SEC Drivers:
- Split the driver into a transport-agnostic core ('sec-core') and
transport-specific ('sec-i2c', 'sec-acpm') modules to support
non-I2C devices
- Merge the 'sec-core' and 'sec-irq' modules to reduce memory
consumption
- Move internal APIs to a private header to clean up the public API
- Improve code style by sorting includes, cleaning up headers,
sorting device tables, and using helper macros like
'dev_err_probe()', 'MFD_CELL', and 'REGMAP_IRQ_REG'
- Make regmap configuration for s2dos05/s2mpu05 explicit to improve
clarity
- Rework platform data and regmap instantiation to use OF match data
instead of a large switch statement
ROHM BD96801/2:
- Prepare the driver for new models by separating chip-specific data
into its own structure
- Drop IC name prefix from IRQ resource names in both the MFD and
regulator drivers for simplification
Broadcom BCM590xx:
- Refactor the regulator driver to store descriptions in a table to
ease support for new chips
- Rename BCM59056-specific data to prepare for the addition of other
regulators
- Use 'dev_err_probe()' for cleaner error handling
Exynos ACPM:
- Correct kerneldoc warnings and use the conventional 'np' argument
name
General MFD:
- Convert 'aat2870' and 'tps65010' to use the per-client debugfs
directory provided by the I2C core
- Convert 'sm501', 'tps65010' and 'ucb1x00' to use the new GPIO line
value setter callbacks
- Constify 'regmap_irq_chip' and other structures in '88pm886' to
move data to read-only sections
BCM590xx:
- Drop the unused "id" member from the 'bcm590xx' struct in
preparation for a replacement
Samsung SEC Core:
- Remove forward declarations for functions that no longer exist
SM501:
- Remove the unused 'sm501_find_clock()' function
New Compatibles:
- Google: Add a PMIC child node to the 'google,gs101-acpm-ipc'
binding
- ROHM: Add new bindings for 'rohm,bd96802-regulator' and
'rohm,bd96802-pmic', and add compatibles for BD96805 and BD96806
- Maxim: Add new bindings for 'maxim,max77759-gpio',
'maxim,max77759-nvmem', and the top-level 'maxim,max77759'
- STM: Add 'stm32mp25' compatible to the 'stm32-lptimer' binding
- Broadcom: Add 'bcm59054' compatible
- Atmel/Microchip: Add 'microchip,sama7d65-gpbr' and
'microchip,sama7d65-secumod' compatibles
- Samsung: Add 's2mpg10' compatible to the 'samsung,s2mps11' MFD
binding
- MediaTek: Add compatibles for 'mt6893' (scpsys), 'mt7988-topmisc',
and 'mt8365-infracfg-nao'
- Qualcomm: Add 'qcom,apq8064-mmss-sfpb' and 'qcom,apq8064-sps-sic'
syscon compatibles
Refactoring & Cleanup:
- Convert Broadcom BCM59056 devicetree bindings to YAML and split
them into MFD and regulator parts
- Convert the Microchip AT91 secumod binding to YAML
- Drop unrelated consumer nodes from binding examples to reduce bloat
- Correct indentation and style in various DTS examples"
* tag 'mfd-next-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (81 commits)
mfd: maxim: Correct Samsung "Electronics" spelling in copyright headers
mfd: maxim: Correct Samsung "Electronics" spelling in headers
mfd: sm501: Remove unused sm501_find_clock
mfd: 88pm886: Constify struct regmap_irq_chip and some other structures
dt-bindings: mfd: syscon: Add mediatek,mt8365-infracfg-nao
mfd: sprd-sc27xx: Fix wakeup source leaks on device unbind
mfd: rt5033: Fix wakeup source leaks on device unbind
mfd: max8925: Fix wakeup source leaks on device unbind
mfd: max77705: Fix wakeup source leaks on device unbind
mfd: max77541: Fix wakeup source leaks on device unbind
mfd: max14577: Fix wakeup source leaks on device unbind
mfd: as3722: Fix wakeup source leaks on device unbind
mfd: 88pm886: Fix wakeup source leaks on device unbind
dt-bindings: mfd: Correct indentation and style in DTS example
dt-bindings: mfd: Drop unrelated nodes from DTS example
dt-bindings: mfd: syscon: Add qcom,apq8064-sps-sic
dt-bindings: mfd: syscon: Add qcom,apq8064-mmss-sfpb
mfd: stmpe-spi: Correct the name used in MODULE_DEVICE_TABLE
dt-bindings: mfd: syscon: Add mt7988-topmisc
mfd: exynos-lpass: Fix another error handling path in exynos_lpass_probe()
...
|
||
|
Linus Torvalds
|
ec71f661a5 |
soc: devicetree updates for 6.16
There are 11 newly supported SoCs, but these are all either new
variants of existing designs, or straig reuses of the existing
chip in a new package:
- RK3562 is a new chip based on the old Cortex-A53 core, apparently
a low-cost version of the Cortex-A55 based RK3568/RK3566.
- NXP i.MX94 is a minor variation of i.MX93/i.MX95 with a different
set of on-chip peripherals.
- Renesas RZ/V2N (R9A09G056) is a new member of the larger RZ/V2 family
- Amlogic S6/S7/S7D
- Samsung Exynos7870 is an older chip similar to Exynos7885
- WonderMedia wm8950 is a minor variation on the wm8850 chip
- Amlogic s805y is almost idential to s805x
- Allwinner A523 is similar to A527 and T527
- Qualcomm MSM8926 is a variant of MSM8226
- Qualcomm Snapdragon X1P42100 is related to R1E80100
There are also 65 boards, including reference designs for the chips
above, this includes
- 12 new boards based on TI K3 series chips, most of them from
Toradex
- 10 devices using Rockchips RK35xx and PX30 chips
- 2 phones and 2 laptops based on Qualcomm Snapdragon designs
- 10 NXP i.MX8/i.MX9 boards, mostly for embedded/industrial uses
- 3 Samsung Galaxy phones based on Exynos7870
- 5 Allwinner based boards using a variety of ARMv8 chips
- 9 32-bit machines, each based on a different SoC family
Aside from the new hardware, there is the usual set of cleanups and
newly added hardware support on existing machines, for a total of 965
devicetree changesets.
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Merge tag 'soc-dt-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC devicetree updates from Arnd Bergmann:
"There are 11 newly supported SoCs, but these are all either new
variants of existing designs, or straight reuses of the existing chip
in a new package:
- RK3562 is a new chip based on the old Cortex-A53 core, apparently a
low-cost version of the Cortex-A55 based RK3568/RK3566.
- NXP i.MX94 is a minor variation of i.MX93/i.MX95 with a different
set of on-chip peripherals.
- Renesas RZ/V2N (R9A09G056) is a new member of the larger RZ/V2
family
- Amlogic S6/S7/S7D
- Samsung Exynos7870 is an older chip similar to Exynos7885
- WonderMedia wm8950 is a minor variation on the wm8850 chip
- Amlogic s805y is almost idential to s805x
- Allwinner A523 is similar to A527 and T527
- Qualcomm MSM8926 is a variant of MSM8226
- Qualcomm Snapdragon X1P42100 is related to R1E80100
There are also 65 boards, including reference designs for the chips
above, this includes
- 12 new boards based on TI K3 series chips, most of them from
Toradex
- 10 devices using Rockchips RK35xx and PX30 chips
- 2 phones and 2 laptops based on Qualcomm Snapdragon designs
- 10 NXP i.MX8/i.MX9 boards, mostly for embedded/industrial uses
- 3 Samsung Galaxy phones based on Exynos7870
- 5 Allwinner based boards using a variety of ARMv8 chips
- 9 32-bit machines, each based on a different SoC family
Aside from the new hardware, there is the usual set of cleanups and
newly added hardware support on existing machines, for a total of 965
devicetree changesets"
* tag 'soc-dt-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (956 commits)
MAINTAINERS, mailmap: update Sven Peter's email address
arm64: dts: renesas: rzg3e-smarc-som: Reduce I2C2 clock frequency
arm64: dts: nuvoton: Add pinctrl
ARM: dts: samsung: sp5v210-aries: Align wifi node name with bindings
arm64: dts: blaize-blzp1600: Enable GPIO support
dt-bindings: clock: socfpga: convert to yaml
arm64: dts: rockchip: move rk3562 pinctrl node outside the soc node
arm64: dts: rockchip: fix rk3562 pcie unit addresses
arm64: dts: rockchip: move rk3528 pinctrl node outside the soc node
arm64: dts: rockchip: remove a double-empty line from rk3576 core dtsi
arm64: dts: rockchip: move rk3576 pinctrl node outside the soc node
arm64: dts: rockchip: fix rk3576 pcie unit addresses
arm64: dts: rockchip: Drop assigned-clock* from cpu nodes on rk3588
arm64: dts: rockchip: Add missing SFC power-domains to rk3576
Revert "arm64: dts: mediatek: mt8390-genio-common: Add firmware-name for scp0"
arm64: dts: mediatek: mt8188: Address binding warnings for MDP3 nodes
arm64: dts: mt6359: Rename RTC node to match binding expectations
arm64: dts: mt8365-evk: Add goodix touchscreen support
arm64: dts: mediatek: mt8188: Add missing #reset-cells property
arm64: dts: airoha: en7581: Add PCIe nodes to EN7581 SoC evaluation board
...
|
||
|
Linus Torvalds
|
f79749a8e4 |
soc: defconfig updates for 6.16
The usual defconfig updates enable configuration options for drivers that got added. A few SoC specific options are enabled in Kconfig files instead, in place of the defconfig files. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmg51Z0ACgkQmmx57+YA GNmQCQ/+KjqUL7oKPU4DffpymcPpPQbMuw6mgcxOI+d+JDeCp63TyM8+goaxJyNc fRiyliaqjIiBvKprGqp8WdpB9lNK6YNzMKbnA6V21+xh28myHsNjs+DWphQLEtuo 316x+MJuK1pqxhBQuFWj7L+IOimu6QAK+btqHKrGKA1IGTqmSA5tEbp5IboZIk7p fSIGNdPu53W3XJKrK1jhGFQCXlYJ0lmX6n5BpJTfiVKQ7lAQQ9tqCS0xAAdMkFc7 Jr2LeWZUXvaZ5kQpY7hnjVlnZu8zs2c1IvLsy4UH3WOJ1m3tuJK2FhLwtrdzN2du DidVm3tvIvIQsXjoA2Ni572jdrTiJP0LlzzmTn/tWoLIujJAEDTzqNhmJywQUgVa 6f6xsfNcang8CYxkRvjRXslKEnl62hI1H7vjGl1y6Ft0bwFtThqG9DmwMhjGVviw yruQL4yYTK2lmumB7lImS/Wk2Wv/UPJeyc18nk2YMTB3zSYJ2p9zvnqiYYBZ7rdk 7PbfkHHLt3JgRrQjGm9ohiAcUQ/4ePn7MYcw37LF5NPseSBlabwZMkWxBQYcIzJ9 AoJeV7i/5yx4Z0ZNhIvaFknkNCvIg18K+GS6znGKHVVTRujfdplALbnnpHmyiu2a xdup3hwT5XEckYHIO2rsPaZU5eSZO7TIfJCWJ8bCL19c4TRrT2g= =X4Kl -----END PGP SIGNATURE----- Merge tag 'soc-defconfig-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull SoC defconfig updates from Arnd Bergmann: "The usual defconfig updates enable configuration options for drivers that got added. A few SoC specific options are enabled in Kconfig files instead, in place of the defconfig files" * tag 'soc-defconfig-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: arm64: defconfig: enable ACPM protocol and Exynos mailbox arm64: defconfig: Enable configs for MediaTek Genio EVK boards arm64: defconfig: mediatek: enable PHY drivers arm64: defconfig: Enable Rockchip SAI and ES8328 arm64: defconfig: Add Toradex Embedded Controller config arm64: defconfig: Enable TPIC2810 GPIO expander riscv: defconfig: spacemit: enable clock controller driver for SpacemiT K1 arm64: defconfig: Enable TMP102 as module arm64: defconfig: Enable hwspinlock and eQEP for K3 arm64: defconfig: Add CDNS_DSI and CDNS_PHY config riscv: defconfig: spacemit: enable gpio support for K1 SoC arm64: defconfig: Enable IPQ5424 RDP466 base configs riscv: Enable PM_GENERIC_DOMAINS for T-Head SoCs |
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Linus Torvalds
|
11147c16a6 |
pwm: Changes for v6.16-rc1
This time around the pwm changes for the next release contain three new drivers (loongson, mc33xs2410 and rzg2l-gpt) and the usual collection of cleanups in both the core and drivers, support for new variants in existing drivers, conversion of dt bindings to yaml and documentation updates. -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEEP4GsaTp6HlmJrf7Tj4D7WH0S/k4FAmgzfgYACgkQj4D7WH0S /k5nJggAoGbk5rGkAMzTNvrQxJLkS2MFQclHyiW+QQu3pOmIcK9rDYP7GI7LNHl5 PBfFGkeWmabdVyMwej87kNarrHLQxHvCfS8Ooc1rGYgaARhJhE2N2/xKLxNQPnhe ZL95O6jcubdllOdHpaWHGaMkPvw4QVMZD9uRuy7ikuf+EiuUhqsqdMQix3x6RXc4 43XLJ1N5SNeHDdF8LVNEwnNwzYFjtLK94dEajPPw+EsiHQ/DyAEohl3vA6k4duxX OnN5BA39SadBWLD4zZLj8LWZC38/1mEx+FUat5ub2q/Buj2/2rxg60Gp+0jyrDMK 44t3wlIM/VHpTzLN1Zh1UpY0bM8eIg== =Y7Ef -----END PGP SIGNATURE----- Merge tag 'pwm/for-6.16-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/ukleinek/linux Pull pwm updates from Uwe Kleine-König: "This time around the pwm changes for the next release contain three new drivers (loongson, mc33xs2410 and rzg2l-gpt) and the usual collection of cleanups in both the core and drivers, support for new variants in existing drivers, conversion of dt bindings to yaml and documentation updates. Thanks for contributions and reviews go to Alexey Charkov, AngeloGioacchino Del Regno, Bartosz Golaszewski, Biju Das, Binbin Zhou, Dan Carpenter, Dimitri Fedrau, Geert Uytterhoeven, George Stark, Huacai Chen, Juxin Gao, Krzysztof Kozlowski, Kuninori Morimoto, Laurent Pinchart, Neil Armstrong, Nuno Sá, Rob Herring, and Trevor Gamblin" * tag 'pwm/for-6.16-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/ukleinek/linux: (39 commits) dt-bindings: timer: renesas,tpu: remove binding documentation pwm: adp5585: make sure to include mod_devicetable.h pwm: Tidyup PWM menu for Renesas pwm: Restore alphabetic ordering in Kconfig and Makefile pwm: Formally describe the procedure used to pick a hardware waveform setting pwm: Let pwm_set_waveform_might_sleep() return 0 instead of 1 after rounding up pwm: Let pwm_set_waveform_might_sleep() fail for exact but impossible requests ARM: shmobile: defconfig: Enable more support for RZN1D-DB/EB arm64: defconfig: Add Renesas MSIOF sound support arm64: defconfig: Enable Renesas RZ/G2L GPT config pwm: add support for NXPs high-side switch MC33XS2410 dt-bindings: pwm: add support for MC33XS2410 pwm: rzg2l-gpt: Accept requests for too high period length dt-bindings: pwm: vt8500-pwm: Convert to YAML dt-bindings: pwm: mediatek,pwm-disp: Add compatible for MT6893 pwm: Fix various formatting issues in kernel-doc pwm: Add support for RZ/G2L GPT dt-bindings: pwm: Add RZ/G2L GPT binding pwm: Better document return value of pwm_round_waveform_might_sleep() pwm: loongson: Fix an error code in probe() ... |
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Linus Torvalds
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14418ddcc2 |
This update includes the following changes:
API: - Fix memcpy_sglist to handle partially overlapping SG lists. - Use memcpy_sglist to replace null skcipher. - Rename CRYPTO_TESTS to CRYPTO_BENCHMARK. - Flip CRYPTO_MANAGER_DISABLE_TEST into CRYPTO_SELFTESTS. - Hide CRYPTO_MANAGER. - Add delayed freeing of driver crypto_alg structures. Compression: - Allocate large buffers on first use instead of initialisation in scomp. - Drop destination linearisation buffer in scomp. - Move scomp stream allocation into acomp. - Add acomp scatter-gather walker. - Remove request chaining. - Add optional async request allocation. Hashing: - Remove request chaining. - Add optional async request allocation. - Move partial block handling into API. - Add ahash support to hmac. - Fix shash documentation to disallow usage in hard IRQs. Algorithms: - Remove unnecessary SIMD fallback code on x86 and arm/arm64. - Drop avx10_256 xts(aes)/ctr(aes) on x86. - Improve avx-512 optimisations for xts(aes). - Move chacha arch implementations into lib/crypto. - Move poly1305 into lib/crypto and drop unused Crypto API algorithm. - Disable powerpc/poly1305 as it has no SIMD fallback. - Move sha256 arch implementations into lib/crypto. - Convert deflate to acomp. - Set block size correctly in cbcmac. Drivers: - Do not use sg_dma_len before mapping in sun8i-ss. - Fix warm-reboot failure by making shutdown do more work in qat. - Add locking in zynqmp-sha. - Remove cavium/zip. - Add support for PCI device 0x17D8 to ccp. - Add qat_6xxx support in qat. - Add support for RK3576 in rockchip-rng. - Add support for i.MX8QM in caam. Others: - Fix irq_fpu_usable/kernel_fpu_begin inconsistency during CPU bring-up. - Add new SEV/SNP platform shutdown API in ccp. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEn51F/lCuNhUwmDeSxycdCkmxi6cFAmgz47AACgkQxycdCkmx i6fvKRAAr4Xa903L0r1Q1P1alQqoFFCqimUWeH72m68LiWynHWi0lUo0z/+tKweg mnPStz7/Ha9HRHJjdNCMPnlJqXQDkuH3bIOuBJCwduDuhHo9VGOd46XGzmGMv3gb HKuZhI0lk7pznK3CSyD/2nHmbDCHD+7feTZSBMoN9mm875+aSoM6fdxgak8uPFcq KbB1L+hObTn2kAPSqRrNOR8/xG2N7hdH8eax7Li+LAtqYNVT5HvWVECsB/CKRPfB sgAv3UTzcIFapSSHUHaONppSeoqPAIAeV7SdQhJvlT+EUUR/h/B6+D9OUQQqbphQ LBalgTnqMKl0ymDEQFQ6QyYCat9ZfNmDft2WcXEsxc8PxImkgJI1W3B8O51sOjbG 78D8JqVQ96dleo4FsBhM2wfG0b41JM6zU4raC4vS7a3qsUS+Q1MpehvcS1iORicy SpGdE8e7DLlxKhzWyW1xJnbrtMZDC7Sa2hUnxrvP0/xOvRhChKscRVtWcf0a5q7X 8JmuvwVSOJuSbQ3MeFbQvpo5lR9+0WsNjM6e9miiH6Y7vZUKmWcq2yDp377qVzeh 7NK6+OwGIQZZExrmtPw2BXwssT9Eg+ks6Y7g2Ne7yzvrjVNfEPY7Cws/5w7p8mRS qhrcpbJNFlWgD7YYkmGZFTQ8DCN25ipP8lklO/hbcfchqLE/o1o= =O8L5 -----END PGP SIGNATURE----- Merge tag 'v6.16-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6 Pull crypto updates from Herbert Xu: "API: - Fix memcpy_sglist to handle partially overlapping SG lists - Use memcpy_sglist to replace null skcipher - Rename CRYPTO_TESTS to CRYPTO_BENCHMARK - Flip CRYPTO_MANAGER_DISABLE_TEST into CRYPTO_SELFTESTS - Hide CRYPTO_MANAGER - Add delayed freeing of driver crypto_alg structures Compression: - Allocate large buffers on first use instead of initialisation in scomp - Drop destination linearisation buffer in scomp - Move scomp stream allocation into acomp - Add acomp scatter-gather walker - Remove request chaining - Add optional async request allocation Hashing: - Remove request chaining - Add optional async request allocation - Move partial block handling into API - Add ahash support to hmac - Fix shash documentation to disallow usage in hard IRQs Algorithms: - Remove unnecessary SIMD fallback code on x86 and arm/arm64 - Drop avx10_256 xts(aes)/ctr(aes) on x86 - Improve avx-512 optimisations for xts(aes) - Move chacha arch implementations into lib/crypto - Move poly1305 into lib/crypto and drop unused Crypto API algorithm - Disable powerpc/poly1305 as it has no SIMD fallback - Move sha256 arch implementations into lib/crypto - Convert deflate to acomp - Set block size correctly in cbcmac Drivers: - Do not use sg_dma_len before mapping in sun8i-ss - Fix warm-reboot failure by making shutdown do more work in qat - Add locking in zynqmp-sha - Remove cavium/zip - Add support for PCI device 0x17D8 to ccp - Add qat_6xxx support in qat - Add support for RK3576 in rockchip-rng - Add support for i.MX8QM in caam Others: - Fix irq_fpu_usable/kernel_fpu_begin inconsistency during CPU bring-up - Add new SEV/SNP platform shutdown API in ccp" * tag 'v6.16-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (382 commits) x86/fpu: Fix irq_fpu_usable() to return false during CPU onlining crypto: qat - add missing header inclusion crypto: api - Redo lookup on EEXIST Revert "crypto: testmgr - Add hash export format testing" crypto: marvell/cesa - Do not chain submitted requests crypto: powerpc/poly1305 - add depends on BROKEN for now Revert "crypto: powerpc/poly1305 - Add SIMD fallback" crypto: ccp - Add missing tee info reg for teev2 crypto: ccp - Add missing bootloader info reg for pspv5 crypto: sun8i-ce - move fallback ahash_request to the end of the struct crypto: octeontx2 - Use dynamic allocated memory region for lmtst crypto: octeontx2 - Initialize cptlfs device info once crypto: xts - Only add ecb if it is not already there crypto: lrw - Only add ecb if it is not already there crypto: testmgr - Add hash export format testing crypto: testmgr - Use ahash for generic tfm crypto: hmac - Add ahash support crypto: testmgr - Ignore EEXIST on shash allocation crypto: algapi - Add driver template support to crypto_inst_setname crypto: shash - Set reqsize in shash_alg ... |
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André Draszik
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680ef57915 |
mfd: sec: Split into core and transport (i2c) drivers
As a preparation for adding support for Samsung's S2MPG10, which is connected via SPEEDY / ACPM rather than I2C, split out (move) all I2C-specific driver code into its own kernel module, sec-i2c, and make the existing sec-core module be just the transport-agnostic core driver kernel module. At the same time, update all defconfigs that reference the old kconfig symbol name. While at it, also update file header comments and module description(s) to drop references to 'mfd', and update comments to be C-style, not C++. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: André Draszik <andre.draszik@linaro.org> Link: https://lore.kernel.org/r/20250409-s2mpg10-v4-8-d66d5f39b6bf@linaro.org Signed-off-by: Lee Jones <lee@kernel.org> |
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Arnd Bergmann
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ae006498a0 |
Enable Rockchip SAI and ES8328 modules.
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Arnd Bergmann
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5c9876f9d1 |
MediaTek ARM64 defconfig updates for v6.16
This enables some drivers as modules to enable fully booting
some of the supported MediaTek boards;
In particular, this enables the following drivers as module:
- PHYs for PCIe, HDMI, DSI and DisplayPort for all boards
- MediaTek UART DMA Controller, also for all boards
- MDP3 driver for MT8186/88/95 (Chromebooks and Genio variants)
- Auxiliary ADC for the MT6357/58/59 PMICs found on both Genio EVK
and Chromebooks based on designs with MT8183/86/88/92/95 SoCs
- iTE IT5205 Type-C USB Alternate Mode Passive MUX, found
on both Chromebooks and Genio EVKs with MT8188/95
- Richtek RT1715 Type-C PD Controller, found on all Genio boards
- Himax HX8279 DSI panel DriverIC and KD070FHFID015 panel, found
on various revisions of the Genio Evaluation Kit boards.
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Merge tag 'mtk-defconfig-for-v6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/defconfig
MediaTek ARM64 defconfig updates for v6.16
This enables some drivers as modules to enable fully booting
some of the supported MediaTek boards;
In particular, this enables the following drivers as module:
- PHYs for PCIe, HDMI, DSI and DisplayPort for all boards
- MediaTek UART DMA Controller, also for all boards
- MDP3 driver for MT8186/88/95 (Chromebooks and Genio variants)
- Auxiliary ADC for the MT6357/58/59 PMICs found on both Genio EVK
and Chromebooks based on designs with MT8183/86/88/92/95 SoCs
- iTE IT5205 Type-C USB Alternate Mode Passive MUX, found
on both Chromebooks and Genio EVKs with MT8188/95
- Richtek RT1715 Type-C PD Controller, found on all Genio boards
- Himax HX8279 DSI panel DriverIC and KD070FHFID015 panel, found
on various revisions of the Genio Evaluation Kit boards.
* tag 'mtk-defconfig-for-v6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux:
arm64: defconfig: Enable configs for MediaTek Genio EVK boards
arm64: defconfig: mediatek: enable PHY drivers
Link: https://lore.kernel.org/r/20250520114356.1194450-2-angelogioacchino.delregno@collabora.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Arnd Bergmann
|
a34a3ddc6b |
One more Qualcomm Arm64 defconfig update for v6.16
Enable global clock controller and TLMM pinctrl drivers for IPQ5424 to make this boot. -----BEGIN PGP SIGNATURE----- iQJJBAABCAAzFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmgr7f0VHGFuZGVyc3Nv bkBrZXJuZWwub3JnAAoJEAsfOT8Nma3FjsgP/Rz5VWfsMwCZejAub3yHEFA/HVcy U1JYYlNXl6BBPV8ta6LhC5AkhF8DMaKw850spzog1nDKdTdnI7jNU70ouprJW8G1 mUQa1pM/VD5KyWeF67WH9sl9p/kcHSxyxWoIfpXbZ43cvGZ+bCk8dNGS6wMJJa9h ebjpQIFEX8tSPm+HnQuW9uExE0UJD/1zeB5f8Nr6YUv1J1P/Z1WHst2z4OY41atL aiNh/uaAWhqad6C6JWcvrFS2+O2dY3ZbB3n8NhgDM1pW6d9gFnRXS+NaE/zc4PtN GqSEo9wgxLJayvHfc5pp/glLqwq8G948IGVLN3aXl+ZZfsSJRnOWEwm5iHmjAQaW kFxH4ePDpctueiiMkxeqRRxt9IzLmoVc8JrQcpsHTECAJEsTx1kqzoLzPDy+ZUeK gbU+I1HmNRY+cIl916ShocF1MLfLgDnUimbWJg3+cfXi44EKsvvh0OHUKsePGo68 wKmQXEYM5w8oR4caQIYaARkRSwTD9MxApUZK5PLWzAXepIGUkULKFyyh65eA1jya CL4UtI76AMVHqXpfGth7p3g4i3K6h9ZGOfb9dVKBHnsdbZmbvfo6tzg9tiD5UV52 lPvwG3dpN8/YCj85J08PYQZYDTCZ8VVZseRWFctIHf+yFyf4sQxrJwfMuMrA7bQy gTdp2o4Ut/wxKIjC =sw/L -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmgvA6IACgkQmmx57+YA GNnrbA/+IXEZjtmuEV6o470/Jghi2f6GzSqQ+AXXXlayvSXspP25odjAFLjYWxwC MTlNERTktsJb2HffClhK+0kmcKRyy09edkjsfdZI0HJ9OpDnnsd+4CsHhxNQs/IF 0Xz2/zpxsKwywlV5Av4MP7sT0YdWH8PnlwMZSczWc1cckD07zyL5drwpch7gJsSm pJQM7MCmDdiFZKjSji8mzveBFyOCiaKHtWrqEI2ZPxhbb2jpch3qaBNJgW1rvIZa Art4niZHoDMgSlI2RrYdXNr8oG9gayCchFy3FxhGhtqoeEZ/U2vNdHJOgAWDxLuL 1HryRst1H/1zzf3Xl/XWpz6xaa1vBQromSzREh/XlpCE48MymgujLNhBBAZM/SDP sP2dW6Es1YL8O8BdyfKG/T61JNTj9o5aORmvAkiEtskfLc9AzPeizyfRmmHOqQru 2yqRhF+R6I5ofko9BXVOWwXKOl2sKz197iTCmxOsh1U9u3old4ea/F60yKJlAc2c 70zMmyPAXj3RBnwuo8FKFqt2v/LSVlSQbNGow+MO9mxHqtMiARG59LrlPex+pEHD qe/i61TbXqPTzbRVDM1Q5oCoRAy2oI0RpoB/YX3CUGZQjBy191RmD95RBJPDSzMx ONmA6BeUPGxVZoBaBsgsJNwBLhMecrDXcO8GqvpPydTpSDVFVVM= =HAVp -----END PGP SIGNATURE----- Merge tag 'qcom-arm64-defconfig-for-6.16-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/defconfig One more Qualcomm Arm64 defconfig update for v6.16 Enable global clock controller and TLMM pinctrl drivers for IPQ5424 to make this boot. * tag 'qcom-arm64-defconfig-for-6.16-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: arm64: defconfig: Enable IPQ5424 RDP466 base configs Link: https://lore.kernel.org/r/20250520025119.40021-1-andersson@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Fabio Estevam
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6c9ab81187
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arm64: defconfig: Ensure CRYPTO_CHACHA20_NEON is selected
Since commit |
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Tudor Ambarus
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93b07587bb
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arm64: defconfig: enable ACPM protocol and Exynos mailbox
Enable the Samsung Exynos ACPM protocol and its transport layer, the Exynos mailbox driver. Samsung Exynos platforms implement ACPM to provide support for PMIC, clock frequency scaling, clock configuration and temperature sensors. Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20250207-gs101-acpm-dt-v4-4-230ba8663a2d@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250513101754.23158-2-krzysztof.kozlowski@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Arnd Bergmann
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e87c7478a3 |
TI K3 defconfig updates for v6.16
- Enable Cadence DSI and PHY driver support for DSI support on BeagleBone-AI64, BeaglePlay, BeagleY-AI, All TI EVMs etc. - Enable hardware spinlock and Quadrature Encoder Pulse (QEP) support for AM64-SK and other boards. - Enable TMP102 driver to support Phytec phyCORE-AM68x/TDA4x and the phyGATE-Tauri-L-iMX8MM - Enable TPIC2810 for AM64-SK LED GPIO control. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEE+KKGk1TrgjIXoxo03bWEnRc2JJ0FAmgiA/MACgkQ3bWEnRc2 JJ29SxAAmRZgxBJ3/ZS+b5Tv///bWnbpZPZVSbGfT1GZO26kHw7gDHI7dIdAPwqv yJjLMFjPZeR0f79GB6b74Q1vx+GvA27jwDsW6wrufq+CoKub85xST+nSUlsqNX9O KlGauSgBEJYqC5Y6vmQcVqsYcZkb8PONJ2cGsoP+wVZfICPf8RReOldSqjpjdVA/ AsUuvIsj/KU51x8v+gKZvJKI6Lz/GQihX4vZDPZGBkp4NMFhA3uXTTDZh8MBhVE0 IrIMFHyxGS04k2IjR/96JI8eGalmeU7g9IoZXG0FLub1gP6sSuTEEMxzuyeWYyRc 1Lf6hN5m/GO4FhVJ6Yn9Yj/BKdTYpoLONXpP9vvld5+CzC/SFzmMICRPe2MgPRB6 M6cvsrd2smYmZyabbUmMUeu5a8QRfv5M/fR4v2iRyLMe20I+oXyNp0SvhVfp/zsT E8hHTsu7PQ7qHG/OxEvqYZXgUoRluCW/nMGNziwj0wtq12Cvdw38qENj7NcIt1a/ fuw7QsAkc97kEmQM39OGDgwtreA9Yintj4/cRjzTvS7fl6hb5JIg/oO+I11dOLcG OUoyZDP1JdEgaxgn0zTOaL6EIcMtxngvlgTS6JYPkTfgUFxYFRN6wqOMScrbDD47 ij+wwv+n4CXIB2njJtPQ7hwjpxqmQyNFMjbcrFzlcC/bTN2SoLY= =B+nK -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmguCE0ACgkQmmx57+YA GNk4EA//clYk+vPVbvDuBhNtBbn2A0/HFFFdYksDgrrpk0l3O9YKPzWM0wYK3f/v aiGgeTST6bS9AGi5L26uV4uIMj22YvkyRWdFl6zltqLJ/U537LEFCuMQtOK1LE7e +AbDUJxmt+pcEfz0tVEN7bR2nBjAsLZTHYWRL5lOsOer2uHMsNr4AoCCxGg0gEOe b/t9B12Cik0jEpIUOMZoup5HhdDo7XRreevTDw4Bpbl7zi8WDd8yZZJycCaTK9ks 8qgViaFoszokr4W2F2DOJNIbTOe6fEYsaR7L/3dRy9ArlGEJCBlX8iTZ/fUUyhOc yvA95erwC1jn8jyxCZr2pAs5styE2V3DGoHAg0rQnWIRm6NYsI899cFlu2/37bNS vl25rnY74CFo1+06lfizvCiA5EKcsKD6Z7/A0IzbXd9uhIU56qjd+eUP6BwNqCCN gkdWtOvGjIxmkiNd5h2ez8YmmA+o7RKtZhvR+jfj1RD1FCilVTgzrQ1UL0h0vnki jPA3J9CgMzFzU8471GsjQh4Qo2kqCXZTtILi4ozM++bI28CyiMSfO1ONK9P7caSh a0lIEXG16V/PiwPNPHq/hbQmAVJ5baQhXtSE9tmvdgbouUXF6sUVAkN0egsTVpCP mdLWL3sEidVmNV4T016Z66jEpxS30jFyp4hV81Zt4EP4skRWHW0= =RRmY -----END PGP SIGNATURE----- Merge tag 'ti-k3-config-for-v6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/defconfig TI K3 defconfig updates for v6.16 - Enable Cadence DSI and PHY driver support for DSI support on BeagleBone-AI64, BeaglePlay, BeagleY-AI, All TI EVMs etc. - Enable hardware spinlock and Quadrature Encoder Pulse (QEP) support for AM64-SK and other boards. - Enable TMP102 driver to support Phytec phyCORE-AM68x/TDA4x and the phyGATE-Tauri-L-iMX8MM - Enable TPIC2810 for AM64-SK LED GPIO control. * tag 'ti-k3-config-for-v6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux: arm64: defconfig: Enable TPIC2810 GPIO expander arm64: defconfig: Enable TMP102 as module arm64: defconfig: Enable hwspinlock and eQEP for K3 arm64: defconfig: Add CDNS_DSI and CDNS_PHY config Link: https://lore.kernel.org/r/20250512144738.dv63fd4fyuly3s44@diocese Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Nícolas F. R. A. Prado
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543e0ecee1
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arm64: defconfig: Enable configs for MediaTek Genio EVK boards
Enable the missing configs to get all devices on the MediaTek Genio 1200, 700, 510 and 350 EVK boards probing, as indicated by the DT kselftest. This includes support for: Genio 1200/700/510/350: * MT6359/MT6357 PMICs Auxiliary ADC Genio 1200/700/510: * MDP3 (video scaling and color space conversion IP block) * ITE IT5205 Type-C USB Alternate Mode Passive MUX * Himax HX8279 controller based KD070FHFID078 DSI panel Genio 700/510: * Richtek RT1715 USB Type-C PD Controller Genio 1200: * MediaTek PCIe PHY * Mediatek MT6360 USB Type-C Port Controller Genio 350: * STARTEK KD070FHFID015 DSI panel * MediaTek UART DMA controller (APDMA) Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250513-genio-defconfig-v1-1-c3862f91b6b2@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> |
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Vignesh Raman
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f52cd248d8
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arm64: defconfig: mediatek: enable PHY drivers
The mediatek display driver fails to probe on mt8173-elm-hana and mt8183-kukui-jacuzzi-juniper-sku16 in v6.14-rc4 due to missing PHY configurations. Commit |
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Fabrice Gasnier
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3cd55c7295 |
arm64: defconfig: enable STM32 LP timer clockevent driver
Enable the STM32 LP timer MFD core and clockevent drivers used on STM32MP257F-EV1 board, for PSCI OSI. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Link: https://lore.kernel.org/r/20250429125133.1574167-6-fabrice.gasnier@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> |