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18 Commits

Author SHA1 Message Date
Sean Anderson
7e1ef5ccb0 arm64: zynqmp: Enable AMS for all boards 
The AMS does not rely on external hardware or features, so it can be
enabled unconditionally.

Signed-off-by: Sean Anderson <sean.anderson@linux.dev>
Link: https://lore.kernel.org/r/20240812215129.3599832-2-sean.anderson@linux.dev
Signed-off-by: Michal Simek <michal.simek@amd.com>
 2024-10-02 09:21:25 +02:00
Michal Simek
8258cf0d4a arm64: zynqmp: Rename i2c?-gpio to i2c?-gpio-grp 
Anything ending with gpio/gpios is taken as gpio phande/description which
is reported as the issue coming from gpio-consumer.yaml schema.
That's why rename the gpio suffix to gpio-grp to avoid name collision.

Link: https://lore.kernel.org/r/94f633e26b7b16cabddb8c7210c2e79208c364da.1704728353.git.michal.simek@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
 2024-01-22 14:10:10 +01:00
Manikanta Guntupalli
ee6c637f38 arm64: zynqmp: Fix open drain warning on ZynqMP 
Mark both GPIO lines as GPIO_OPEN_DRAIN which is required by i2c-gpio DT
binding. Similar change was done by commit 8df80c1801 ("ARM: dts: exynos:
Convert to new i2c-gpio bindings").

Signed-off-by: Manikanta Guntupalli <manikanta.guntupalli@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/a0faf488dde310e1c1c1a676c371e223db6bdca6.1686227712.git.michal.simek@amd.com
 2023-07-10 12:05:16 +02:00
Amit Kumar Mahapatra
1d831cade7 arm64: zynqmp: Set qspi tx-buswidth to 4 
All ZynqMP boards are setting up tx-buswidth to 1. Due to this the
framework only issues 1-1-1 write commands to the GQSPI driver. But the
GQSPI controller is capable of handling 1-4-4 write commands, so updated
the tx-buswidth to 4.
Using all 4 lines will increase the tx data transfer rate, as now the
tx data will be transferred on four lines instead on single line.

Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/1f1b0028106d83aa06e0777e91862a07df100fa1.1684767562.git.michal.simek@amd.com
 2023-06-05 13:15:02 +02:00
Ashok Reddy Soma
f8673fd570 arm64: zynqmp: Fix usb node drive strength and slew rate 
As per design, all input/rx pins should have fast slew rate and 12mA
drive strength. Rest all pins should be slow slew rate and 4mA drive
strength. Fix usb nodes as per this and remove setting of slow slew rate
for all the usb group pins.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/379071f44ceb27a0e32d74e13221640922d989d1.1684767562.git.michal.simek@amd.com
 2023-06-05 13:15:02 +02:00
Michal Simek
c720a1f5e6 arm64: zynqmp: Describe TI phy as ethernet-phy-id 
TI DP83867 is using strapping based on MIO pins. Tristate setup can
influence PHY address. That's why switch description with ethernet-phy-id
compatible string which enable calling reset. PHY itself setups phy address
after power up or reset. Phy reset is done via gpio.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/b49904649a363f40dc9c4d3fa275e42129562082.1684767562.git.michal.simek@amd.com
 2023-06-05 13:15:02 +02:00
Michal Simek
4e4ddd3d1d arm64: zynqmp: Switch to amd.com emails 
Update my and DPs email address to match current setup.

Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/108cbbbab29e13d386d38a779fd582f10844a030.1685443337.git.michal.simek@amd.com
 2023-06-05 13:14:21 +02:00
Michal Simek
255118de76 arm64: zynqmp: Enable AMS on SOM and other zcu10x boards 
AMS is used for monitoring system. Used for measuring voltages and
especially temperatures. Origin interface is IIO but via iio-hwmon it can
be moved to hwmon framework too (done for SOM and zcu100).

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/e1e1621ac1cee7f36ef20606bb3795e130de9609.1683034376.git.michal.simek@amd.com
 2023-05-16 14:50:15 +02:00
Parth Gajjar
37e7894910 arm64: zynqmp: Add mali-400 gpu node for zynqmp 
Add mali-400 gpu node for zynqmp.
Enabled gpu node for xilinx boards.

Signed-off-by: Parth Gajjar <parth.gajjar@amd.com>
Signed-off-by: Vishal Sagar <vishal.sagar@amd.com>
Link: https://lore.kernel.org/r/20230321070619.29440-3-parth.gajjar@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
 2023-05-12 13:23:07 +02:00
Michal Simek
b61c4ff951 arm64: zynqmp: Enable xlnx,zynqmp-dwc3 driver for xilinx boards 
The commit 84770f028f ("usb: dwc3: Add driver for Xilinx platforms")
finally add proper support for Xilinx dwc3 driver. This patch is adding DT
description for it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Michael Tretter <m.tretter@pengutronix.de>
Link: https://lore.kernel.org/r/640a3bc0dc3e32560d3e84c2f78b5ae561396eb0.1628244703.git.michal.simek@xilinx.com
 2021-09-13 08:55:56 +02:00
Michal Simek
31533c2176 arm64: zynqmp: Remove description for 8T49N287 and si5382 chips 
Based on commit 73d677e9f3 ("arm64: dts: zynqmp: Remove si5328 device
nodes") also remove description for clock chips which don't have Linux
driver yet.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/7557288230567fa136ba3edc004d5bfe4f4c6590.1623684253.git.michal.simek@xilinx.com
 2021-09-13 08:55:55 +02:00
Michal Simek
cd28f90bbc arm64: zynqmp: Sync psgtr node location with zcu104-revA 
zcu104-revA has node below pinctrl which is not the same on revC. Sync
location for easier comparison.
Also zc1751-dc1 is not using this position.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/4b691bab5ba83b5352d4669bd54bcdb8273b2156.1623684253.git.michal.simek@xilinx.com
 2021-09-13 08:55:55 +02:00
Michal Simek
56e5460151 arm64: zynqmp: Wire qspi on multiple boards 
Couple of boards have qspi on the board that's why enable controller and
describe them.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/01a69ee6590245b5bee70a2553f6faac0d31ca76.1623684253.git.michal.simek@xilinx.com
 2021-09-13 08:55:55 +02:00
Michal Simek
d65ec93f21 arm64: zynqmp: Add nvmem alises for eeproms 
Use nvmem alias to point to eeprom memory which contains information about
board. The change is done based on discussion in the link below.

Link: https://lore.kernel.org/r/CAL_JsqLMDqpkyg-Q7mUfw-XH67-v068Q6e9wTq2UOoN=0-_coQ@mail.gmail.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/9b860b47ec3ca64340b4d29317e92b667236d7d1.1623684253.git.michal.simek@xilinx.com
 2021-09-13 08:55:54 +02:00
Michal Simek
8b698f1b98 arm64: zynqmp: Add phy description for usb3.0 
usb3.0 requires serdes setting that's why also wire it up.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/cd856e5f87bc967373691d04e79de3d0022ef424.1623684253.git.michal.simek@xilinx.com
 2021-09-13 08:55:53 +02:00
Michal Simek
c821045f18 arm64: zynqmp: Add pinctrl description for all boards 
The commit 1dccb5ec01 ("dt-bindings: pinctrl: Add binding for ZynqMP
pinctrl driver") and commit 8b242ca700 ("pinctrl: Add Xilinx ZynqMP
pinctrl driver support") add support for Xilinx ZynqMP pinctrl driver
that's why describe pins configuration for current boards.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/d8bc42600da85f5a23d977d4b61e6528720573e5.1623684253.git.michal.simek@xilinx.com
 2021-09-13 08:55:52 +02:00
Laurent Pinchart
55563399bb arm64: dts: zynqmp: Wire up the DisplayPort subsystem 
Enable the dpsub device and wire it up to the PS-GTR PHY lanes routed to
the DisplayPort connector.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/9769d4d103b6eb75e3324825117f6832a746004e.1611232558.git.michal.simek@xilinx.com
 2021-02-01 10:40:37 +01:00
Michal Simek
127b856f67 arm64: dts: zynqmp: Add description for zcu104 revC 
Xilinx ZynqMP zcu104 revC and newer board revisions have different i2c
structure compare to revA. The rest of the board is the same from software
perspective.
Also enable DMAs and QSPI.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/17f68c235ea1ce96c3293ca0cf3178951d6663f7.1611224800.git.michal.simek@xilinx.com
 2021-02-01 10:37:53 +01:00