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20 Commits

Author SHA1 Message Date
Michal Simek
8258cf0d4a arm64: zynqmp: Rename i2c?-gpio to i2c?-gpio-grp 
Anything ending with gpio/gpios is taken as gpio phande/description which
is reported as the issue coming from gpio-consumer.yaml schema.
That's why rename the gpio suffix to gpio-grp to avoid name collision.

Link: https://lore.kernel.org/r/94f633e26b7b16cabddb8c7210c2e79208c364da.1704728353.git.michal.simek@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
 2024-01-22 14:10:10 +01:00
Michal Simek
2da2ac3c8d arm64: xilinx: Put ethernet phys to mdio node 
All zynqmp boards have been already described via mdio node that's why also
convert zc1751. With using mdio node there is an option to add reset
property for the whole mdio bus.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/dc228a27579b48f3e768fcb439d118b4a0f0ef5b.1695040866.git.michal.simek@amd.com
 2023-12-13 16:52:47 +01:00
Manikanta Guntupalli
ee6c637f38 arm64: zynqmp: Fix open drain warning on ZynqMP 
Mark both GPIO lines as GPIO_OPEN_DRAIN which is required by i2c-gpio DT
binding. Similar change was done by commit 8df80c1801 ("ARM: dts: exynos:
Convert to new i2c-gpio bindings").

Signed-off-by: Manikanta Guntupalli <manikanta.guntupalli@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/a0faf488dde310e1c1c1a676c371e223db6bdca6.1686227712.git.michal.simek@amd.com
 2023-07-10 12:05:16 +02:00
Amit Kumar Mahapatra
1d831cade7 arm64: zynqmp: Set qspi tx-buswidth to 4 
All ZynqMP boards are setting up tx-buswidth to 1. Due to this the
framework only issues 1-1-1 write commands to the GQSPI driver. But the
GQSPI controller is capable of handling 1-4-4 write commands, so updated
the tx-buswidth to 4.
Using all 4 lines will increase the tx data transfer rate, as now the
tx data will be transferred on four lines instead on single line.

Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/1f1b0028106d83aa06e0777e91862a07df100fa1.1684767562.git.michal.simek@amd.com
 2023-06-05 13:15:02 +02:00
Ashok Reddy Soma
f8673fd570 arm64: zynqmp: Fix usb node drive strength and slew rate 
As per design, all input/rx pins should have fast slew rate and 12mA
drive strength. Rest all pins should be slow slew rate and 4mA drive
strength. Fix usb nodes as per this and remove setting of slow slew rate
for all the usb group pins.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/379071f44ceb27a0e32d74e13221640922d989d1.1684767562.git.michal.simek@amd.com
 2023-06-05 13:15:02 +02:00
Michal Simek
4e4ddd3d1d arm64: zynqmp: Switch to amd.com emails 
Update my and DPs email address to match current setup.

Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/108cbbbab29e13d386d38a779fd582f10844a030.1685443337.git.michal.simek@amd.com
 2023-06-05 13:14:21 +02:00
Parth Gajjar
37e7894910 arm64: zynqmp: Add mali-400 gpu node for zynqmp 
Add mali-400 gpu node for zynqmp.
Enabled gpu node for xilinx boards.

Signed-off-by: Parth Gajjar <parth.gajjar@amd.com>
Signed-off-by: Vishal Sagar <vishal.sagar@amd.com>
Link: https://lore.kernel.org/r/20230321070619.29440-3-parth.gajjar@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
 2023-05-12 13:23:07 +02:00
Michal Simek
b61c4ff951 arm64: zynqmp: Enable xlnx,zynqmp-dwc3 driver for xilinx boards 
The commit 84770f028f ("usb: dwc3: Add driver for Xilinx platforms")
finally add proper support for Xilinx dwc3 driver. This patch is adding DT
description for it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Michael Tretter <m.tretter@pengutronix.de>
Link: https://lore.kernel.org/r/640a3bc0dc3e32560d3e84c2f78b5ae561396eb0.1628244703.git.michal.simek@xilinx.com
 2021-09-13 08:55:56 +02:00
Michal Simek
a025f01d46 arm64: zynqmp: Add psgtr description to zc1751 dc1 board 
Wire psgtr for zc1751 dc1 board.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/51d9a5e0aa26b0ea79b8823bf3d15f4e2542f927.1623684253.git.michal.simek@xilinx.com
 2021-09-13 08:55:55 +02:00
Michal Simek
cd28f90bbc arm64: zynqmp: Sync psgtr node location with zcu104-revA 
zcu104-revA has node below pinctrl which is not the same on revC. Sync
location for easier comparison.
Also zc1751-dc1 is not using this position.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/4b691bab5ba83b5352d4669bd54bcdb8273b2156.1623684253.git.michal.simek@xilinx.com
 2021-09-13 08:55:55 +02:00
Michal Simek
56e5460151 arm64: zynqmp: Wire qspi on multiple boards 
Couple of boards have qspi on the board that's why enable controller and
describe them.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/01a69ee6590245b5bee70a2553f6faac0d31ca76.1623684253.git.michal.simek@xilinx.com
 2021-09-13 08:55:55 +02:00
Michal Simek
1d4bd118c9 arm64: zynqmp: Add note about UHS mode on some boards 
Add note about UHS mode and add no-1-8-v property to zc1751-dc1 board.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/462b95844e7aedb00768035913265d7af90c3b2f.1623684253.git.michal.simek@xilinx.com
 2021-09-13 08:55:54 +02:00
Michal Simek
7248f5784b arm64: zynqmp: Wire DP and DPDMA for dc1/dc4 
Enable Display Port and Display Port DMA for zc1751 dc1 and dc4.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/dbbd212bcc587e835d6df2f91622f5baa124bff5.1623684253.git.michal.simek@xilinx.com
 2021-09-13 08:55:53 +02:00
Michal Simek
69f8aec4f9 arm64: zynqmp: Add missing mio-bank properties to dc1 and dc5 
Add missing mio-bank properties to zc1751 dc1 and dc5 boards.
The same change was done by commit 63481699d6 ("arm64: dts: zynqmp: Add
missing mio-bank properties to sdhcis").

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/2b2ab31639c706651dfd319f5b6bc59e68f111b6.1623684253.git.michal.simek@xilinx.com
 2021-09-13 08:55:53 +02:00
Michal Simek
a09c2fea11 arm64: zynqmp: Wire psgtr for zc1751-xm015 
Add psgtr description for SATA and USB. Display Port could be also added
but it wasn't tested yet.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/3fb11fdb9ade828fa174379515e45ba02bc17247.1623684253.git.michal.simek@xilinx.com
 2021-09-13 08:55:52 +02:00
Michal Simek
c821045f18 arm64: zynqmp: Add pinctrl description for all boards 
The commit 1dccb5ec01 ("dt-bindings: pinctrl: Add binding for ZynqMP
pinctrl driver") and commit 8b242ca700 ("pinctrl: Add Xilinx ZynqMP
pinctrl driver support") add support for Xilinx ZynqMP pinctrl driver
that's why describe pins configuration for current boards.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/d8bc42600da85f5a23d977d4b61e6528720573e5.1623684253.git.michal.simek@xilinx.com
 2021-09-13 08:55:52 +02:00
Michal Simek
13d21eba78 arm64: zynqmp: Use ethernet-phy as node name for ethernet phys 
Ethernet phys based on devicetree specification should be using
ethernet-phy@ node name instead of pure phy@.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
 2020-01-09 14:48:20 +01:00
Rajan Vaja
9c8a47b484 arm64: dts: xilinx: Add the clock nodes for zynqmp 
Add clock nodes for zynqmp based on CCF.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
 2020-01-09 14:21:39 +01:00
Anurag Kumar Vulisha
df906cf54b arm64: zynqmp: Add dr_mode property to usb node 
This patch adds dr_mode property to the usb node for
zynqmp boards.

Signed-off-by: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
 2019-12-12 15:41:04 +01:00
Michal Simek
e2fc49e198 arm64: zynqmp: Add support for Xilinx zc1751 
Xilinx zc1751 boards is used for silicon validation. Board can be
extended with 5 FMCs/DCs cards to connect various IPs. Describe all
these combinations.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Rob Herring <robh@kernel.org>
 2018-03-08 08:06:53 +01:00